| Verification of configurable processor cores |
| Full text |
Pdf
(79 KB)
|
| Source
|
Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 37th Annual Design Automation Conference
table of contents
Los Angeles, California, United States
Pages: 426 - 431
Year of Publication: 2000
ISBN:1-58113-187-9
|
|
Authors
|
|
Marinés Puig-Medina
|
Tensilica, Inc., 3255-6 Scott Boulevard, Santa Clara, CA
|
|
Gülbin Ezer
|
Tensilica, Inc., 3255-6 Scott Boulevard, Santa Clara, CA
|
|
Pavlos Konas
|
Tensilica, Inc., 3255-6 Scott Boulevard, Santa Clara, CA
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 4, Downloads (12 Months): 13, Citation Count: 4
|
|
|
ABSTRACT
This paper presents a verification methodology for configurable processor cores. The simulation-based approach uses directed diagnostics and pseudo-random program generators both of which are tailored to specific processor instances. A configurable and extensible test-bench serves as the framework for the verification process and offers components necessary for the complete SOC verification. Coverage analysis provides an evaluation of how well a specific design has been exercised, of the breadth of the configuration space explored, and suggests improvements to the process. The results of the analysis show that our methodology achieves good verification coverage of the processor implementation.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
 |
1
|
Aharon Aharon , Dave Goodman , Moshe Levinger , Yossi Lichtenstein , Yossi Malka , Charlotte Metzger , Moshe Molcho , Gil Shurek, Test program generation for functional verification of PowerPC processors in IBM, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.279-285, June 12-16, 1995, San Francisco, California, United States
[doi> 10.1145/217474.217542]
|
| |
2
|
|
 |
3
|
Laurent Fournier , Anatoly Koyfman , Moshe Levinger, Developing an architecture validation suite: application to the PowerPC architecture, Proceedings of the 36th ACM/IEEE conference on Design automation, p.189-194, June 21-25, 1999, New Orleans, Louisiana, United States
[doi> 10.1145/309847.309911]
|
 |
4
|
Daniel Geist , Giora Biran , Tamara Arons , Michael Slavkin , Yvgeny Nustov , Monica Farkas , Karen Holtz , Andy Long , Dave King , Steve Barret, A methodology for the verification of a “system on chip”, Proceedings of the 36th ACM/IEEE conference on Design automation, p.574-579, June 21-25, 1999, New Orleans, Louisiana, United States
[doi> 10.1145/309847.310001]
|
| |
5
|
|
 |
6
|
Anoosh Hosseini , Dimitrios Mavroidis , Pavlos Konas, Code generation and analysis for the functional verification of micro processors, Proceedings of the 33rd annual conference on Design automation, p.305-310, June 03-07, 1996, Las Vegas, Nevada, United States
[doi> 10.1145/240518.240574]
|
| |
7
|
S. Mangelsdorf, R. Gratias, R. Blumberg, and R. Bhatia. Functional Verification of the HP PA 8000 Processor. Hewlett-Packard Journal, 48(4), August 1997.
|
 |
8
|
Jonah McLeod , Nozar Azarakhsh , Glen Ewing , Paul Gingras , Scott Reedstrom , Chris Rowen, Functional verification—real users, real problems, real opportunities (panel), Proceedings of the 36th ACM/IEEE conference on Design automation, p.260-261, June 21-25, 1999, New Orleans, Louisiana, United States
[doi> 10.1145/309847.309925]
|
| |
9
|
Synopsys Inc., Mountain View, California. VeraTM Verification System, User's Manual, 1999.
|
 |
10
|
Scott Taylor , Michael Quinn , Darren Brown , Nathan Dohm , Scot Hildebrandt , James Huggins , Carl Ramey, Functional verification of a multiple-issue, out-of-order, superscalar Alpha processor—the DEC Alpha 21264 microprocessor, Proceedings of the 35th annual conference on Design automation, p.638-643, June 15-19, 1998, San Francisco, California, United States
[doi> 10.1145/277044.277208]
|
CITED BY 4
|
|
Timothy Sherwood , Mark Oskin , Brad Calder, Balancing design options with Sherpa, Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, September 22-25, 2004, Washington DC, USA
|
|
|
|
|
|
|
|
|
|
|