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Verification of configurable processor cores
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 37th Annual Design Automation Conference table of contents
Los Angeles, California, United States
Pages: 426 - 431  
Year of Publication: 2000
ISBN:1-58113-187-9
Authors
Marinés Puig-Medina  Tensilica, Inc., 3255-6 Scott Boulevard, Santa Clara, CA
Gülbin Ezer  Tensilica, Inc., 3255-6 Scott Boulevard, Santa Clara, CA
Pavlos Konas  Tensilica, Inc., 3255-6 Scott Boulevard, Santa Clara, CA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 13,   Citation Count: 4
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ABSTRACT

This paper presents a verification methodology for configurable processor cores. The simulation-based approach uses directed diagnostics and pseudo-random program generators both of which are tailored to specific processor instances. A configurable and extensible test-bench serves as the framework for the verification process and offers components necessary for the complete SOC verification. Coverage analysis provides an evaluation of how well a specific design has been exercised, of the breadth of the configuration space explored, and suggests improvements to the process. The results of the analysis show that our methodology achieves good verification coverage of the processor implementation.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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S. Mangelsdorf, R. Gratias, R. Blumberg, and R. Bhatia. Functional Verification of the HP PA 8000 Processor. Hewlett-Packard Journal, 48(4), August 1997.
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Synopsys Inc., Mountain View, California. VeraTM Verification System, User's Manual, 1999.
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Collaborative Colleagues:
Marinés Puig-Medina: colleagues
Gülbin Ezer: colleagues
Pavlos Konas: colleagues