| COSY communication IP's |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 37th Annual Design Automation Conference
table of contents
Los Angeles, California, United States
Pages: 406 - 409
Year of Publication: 2000
ISBN:1-58113-187-9
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Downloads (6 Weeks): 4, Downloads (12 Months): 19, Citation Count: 28
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 ABSTRACT
The Fsprit/OMI-COSY project defines transaction-levels to set-up the exchange of IP's in separating function from architecture and body-behavior from proprietary interfaces. These transaction-levels are supported by the “COSY COMMUNICATION IPs” that are presented in this paper. They implement onto Systems-On-Chip the extended Kahn Process Network that is defined in COSY for modeling signal processing applications. We present a generic implementation and performance model of these system-level communications and we illustrate specific implementations. They set system communications across software and hardware boundaries, and achieve bus independence through the Virtual Component Interface of the VSI Alliance. Finally, we describe the COSY-VCC flow that supports communication refinement from specification, to performance estimation, to implementation.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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J.Y Brunel et al., ~COSY: a methodology for system design based on reusable hardware & software IP's,>> in: J-Y. Roger (ed.), Technologies for the Information Society, IOS Press, 709-716, 1998
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J.-Y. Brunel , E. A. de Kock , W. M. Kruijtzer , H. J. H. N. Kenter , W. J. M. Smits, Communication refinement in video systems on chip, Proceedings of the seventh international workshop on Hardware/software codesign, p.142-146, March 1999, Rome, Italy
[doi> 10.1145/301177.301511]
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D. Fairbank et al., ~The VSI Alliance: journey from vision to production,>> Electronic Design, vol. 46, no. 1, pp. 86-92, Jan 12 1998.
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G. Martin et al., ~Methodology and technology for design of communications and multimedia products via system-level IP integration,>> DAC, 1998
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E. A. de Kock , W. J. M. Smits , P. van der Wolf , J.-Y. Brunel , W. M. Kruijtzer , P. Lieverse , K. A. Vissers , G. Essink, YAPI: application modeling for signal processing systems, Proceedings of the 37th conference on Design automation, p.402-405, June 05-09, 2000, Los Angeles, California, United States
[doi> 10.1145/337292.337511]
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Peter Clarke, ~Philips extends TriMedia reuse into Nexperia cores>> EE Times, Aug 30,1999
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CITED BY 28
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Sungjoo Yoo , Gabriela Nicolescu , Damien Lyonnard , Amer Baghdadi , Ahmed A. Jerraya, A generic wrapper architecture for multi-processor SoC cosimulation and design, Proceedings of the ninth international symposium on Hardware/software codesign, p.195-200, April 2001, Copenhagen, Denmark
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M. Sgroi , M. Sheets , A. Mihal , K. Keutzer , S. Malik , J. Rabaey , A. Sangiovanni-Vencentelli, Addressing the system-on-a-chip interconnect woes through communication-based design, Proceedings of the 38th conference on Design automation, p.667-672, June 2001, Las Vegas, Nevada, United States
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A. Baghdadi , D. Lyonnard , N. Zergainoh , A. Jerraya, An efficient architecture model for systematic design of application-specific multiprocessor SoC, Proceedings of the conference on Design, automation and test in Europe, p.55-63, March 2001, Munich, Germany
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Vladimir D. Živković , Paul Lieverse, An overview of methodologies and tools in the field of system-level design, Embedded processor design challenges: systems, architectures, modeling, and simulation-SAMOS, Springer-Verlag New York, Inc., New York, NY, 2002
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Wander O.Cesário , Damien Lyonnard , Gabriela Nicolescu , Yanick Paviot , Sungjoo Yoo , Ahmed A.Jerraya , Lovic Gauthier , Mario Diaz-Nava, Multiprocessor SoC Platforms: A Component-Based Design Approach, IEEE Design & Test, v.19 n.6, p.52-63, November 2002
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Férid Gharsalli , Damien Lyonnard , Samy Meftali , Frédéric Rousseau , Ahmed A. Jerraya, Unifying memory and processor wrapper architecture in multiprocessor SoC design, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan
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Ferid Gharsalli , Samy Meftali , Frédéric Rousseau , Ahmed A. Jerraya, Automatic generation of embedded memory wrapper for multiprocessor SoC, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
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Pieter van der Wolf , Erwin de Kock , Tomas Henriksson , Wido Kruijtzer , Gerben Essink, Design and programming of embedded multiprocessors: an interface-centric approach, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 08-10, 2004, Stockholm, Sweden
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Marcello Coppola , Stephane Curaba , Miltos D. Grammatikakis , Riccardo Locatelli , Giuseppe Maruccia , Francesco Papariello, OCCN: a NoC modeling framework for design exploration, Journal of Systems Architecture: the EUROMICRO Journal, v.50 n.2-3, p.129-163, February 2004
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Mohamed-Wassim Youssef , Sungjoo Yoo , Arif Sasongko , Yanick Paviot , Ahmed A. Jerraya, Debugging HW/SW interface for MPSoC: video encoder system design case study, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
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Albert Cohen , Marc Duranton , Christine Eisenbeis , Claire Pagetti , Florence Plateau , Marc Pouzet, Synchronization of periodic clocks, Proceedings of the 5th ACM international conference on Embedded software, September 18-22, 2005, Jersey City, NJ, USA
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Adriano Sarmento , Lobna Kriaa , Arnaud Grasset , Mohamed-Wassim Youssef , Aimen Bouchhima , Frederic Rousseau , Wander Cesario , Ahmed Amine Jerraya, Service dependency graph: an efficient model for hardware/software interfaces modeling and generation for SoC design, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA
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Albert Cohen , Marc Duranton , Christine Eisenbeis , Claire Pagetti , Florence Plateau , Marc Pouzet, N-synchronous Kahn networks: a relaxed model of synchrony for real-time systems, ACM SIGPLAN Notices, v.41 n.1, p.180-193, January 2006
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M. Anouar Dziri , Firaz Samet , Flavio Rech Wagner , Wander O. Cesário , Ahmed A. Jerraya, Combining architecture exploration and a path to implementation to build a complete SoC design flow from system specification to RTL, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
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Youngchul Cho , Ganghee Lee , Sungjoo Yoo , Kiyoung Choi , Nacer-Eddine Zergainoh, Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design, Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum, p.20132, March 03-07, 2003
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Marcello Coppola , Stephane Curaba , Miltos D. Grammatikakis , Giuseppe Maruccia , Francesco Papariello, OCCN: A Network-On-Chip Modeling and Simulation Framework, Proceedings of the conference on Design, automation and test in Europe, p.30174, February 16-20, 2004
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Sang-Il Han , Soo-Ik Chae , Lisane Brisolara , Luigi Carro , Katalin Popovici , Xavier Guerin , Ahmed A. Jerraya , Kai Huang , Lei Li , Xiaolang Yan, Simulink®-based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation, Integration, the VLSI Journal, v.42 n.2, p.227-245, February, 2009
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