An instruction-level functionally-based energy estimation model for 32-bits microprocessors

ABSTRACT

The paper presents a novel strategy aimed at modeling the instruction energy consumption of 32-bits microprocessors. The proposed instruction-level pow er model is founded on afunctional decomposition of the activities accomplished by a generic microprocessor and exhibits significant generalization capabilities. It allo ws estimation of the pow er figures of the en tire instruction-set starting from the analysis of a subset, as w ell as to po w er characterize new processors using the model obtained by considering other microprocessors.

REFERENCES

• 1: T.Sato, M.Nagamatsu and H.Tago, "Power and performance simulator: ESP and its application for 100MIPS~W class RISC design," Proc. of 1994 IEEE Symposium on Low Power Electronic, pp. 46-47, San Diego, CA, Oct. 1994.
• 2: P.W.Ong and R.H.Yan, "Power-conscious software design: a framework for modeling software on hardware," Proc. of 1994 IEEE Symposium on Low Power Electronic, pp. 36-37, San Diego, CA, Oct. 1994.
• 3: P.Landam and J.Rabaey, "Black-box capacitance models for architectural power analysis," Proc. of Int. Workshop on Low Power Design, pp 165-170, Napa, CA, April 1994.
• 4: Vivek Tiwari , Sharad Malik , Andrew Wolfe, Power analysis of embedded software: a first step towards software power minimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.437-445, Dec. 1994 [doi>10.1109/92.335012]
• 5: V. Tiwari and M.T.-C. Lee, "Power analysis of a 32-bit Erabedded Microcontroller," VLSI Design Journal, 1996.
• 6: Software Power Estimation and Optimization for High Performance, 32-bit Embedded Processors, Proceedings of the International Conference on Computer Design, p.328, October 05-05, 1998
• 7: V. Tiwari, S. Malik, and A. Wolfe, "Power Analysis of the Intel ~86DX2," Computer Engineering Technical Report No. CE-M94-5, Princeton University, Jun. 1994.
• 8: V. Tiwari, M.T.C. Lee M.Fujita and D. Maheshwari, "Power Analysis of the SPARClite MB8693~," Technical Report FLA-CAD-94-01, Fujitsu Labs of America, Oct. 1994.
• 9: J. Russell, "Power Consumption and Execution Time for the Various Instructions: JF and HD processors results," http://www, ece. ut exas. edu /~j russell/p ower_inst r
• 10: PEOPLE (Power Estimation for Fast Exploration of Embedded Systems) ESPRIT-ESD project n.26769, Technical Report D3.3.1.
• 11: C. Brandolese, W. Fornaciari, F. Salice, D. Sciuto "Fast Software-Level Power Estimation for Design Space Exploration," Politecnico di Milano, Tech. Report 99.62, 1999.

INDEX TERMS

Primary Classification:
  J. Computer Applications

Additional Classification:
  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: Instruction set design (e.g., RISC, CISC, VLIW)

General Terms:
Design, Experimentation, Measurement, Performance, Theory