Predicting performance potential of modern DSPs

ABSTRACT

High-level development tools for digital signal processors (DSPs) remain unable to extract optimal performance from them without the designer's in-depth knowledge of the architecture. In this paper we describe our approach to Retargetable Estimation and show how and why it can be effective in quickly predicting and guiding toward hand-optimized performance of moderns DSPs for a given application described in a high-level language. We also contrast the advantages of this scheme with those of a full-featured optimizing compiler.

REFERENCES

• 1: Jennifer Eyre , Jeff Bier, DSP Processors Hit the Mainstream, Computer, v.31 n.8, p.51-59, August 1998 [doi>10.1109/2.707617]
• 2: Texas Instruments. TMS320C6000 CPU and instruction set reference guide http://www.ti.com/sc/psheets/spru 189d/spru 189d.pdf, 1997.
• 3: J. Bier, "Processors for DSP--the options multiply," The Embedded Processor Forum. MicroDesign Resources, 1998.
• 4: Texas Instruments. TMS320C62x Programmer's Guide. http://wwws.ti.com/sc/psheets/spru 198c/spru 198c.pdf, 1999.
• 5: LSI Logic (formerly ZSP Corporation), The ZSP164xx Programmer's Reference Manual. 1997.
• 6: Naji Ghazal , Richard Newton , Jan Rabaey, Retargetable estimation scheme for DSP architecture selection, Proceedings of the 2000 conference on Asia South Pacific design automation, p.485-490, January 2000, Yokohama, Japan [doi>10.1145/368434.368766]
• 7: M. Yamguchi, et. al., "Architecture evaluation based on datapath structure and parallel constraint." Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 503-08, January 1997.
• 8: Jie Gong , Daniel D. Gajski , Alexandru Nicolau, Performance evaluation for application-specific architectures, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.4, p.483-490, Dec. 1995 [doi>10.1109/92.475967]
• 9: A. Fauth , J. Van Praet , M. Freericks, Describing instruction set processors using nML, Proceedings of the 1995 European conference on Design and Test, p.503, March 06-09, 1995
• 10: George Hadjiyiannis , Silvina Hanono , Srinivas Devadas, ISDL: an instruction set description language for retargetability, Proceedings of the 34th annual conference on Design automation, p.299-302, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266108]
• 11: V. Zivojnovic, et al., "LISA-machine description language and generic machine model for HW/SW co-design." VLSI Signal Processing, IX, pp. 127-36, 1996.
• 12: Ashok Sudarsanam , Sharad Malik, Code optimization libraries for retargetable compilation for embedded digital signal processors, 1998
• 13: Silvina Hanono , Srinivas Devadas, Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator, Proceedings of the 35th annual conference on Design automation, p.510-515, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277184]
• 14: Vojin Zivojnović , Steven Tjiang , Heinrich Meyr, Compiled Simulation of Programmable DSP Architectures, Journal of VLSI Signal Processing Systems, v.16 n.1, p.73-80, May 1997 [doi>10.1023/A:1007916402263]
• 15: Stanford Compiler Group. The SUIF Library, version 1.0, http ://suif. stanford.edu/suif/suifl/docs/suif....toc.html 1994.
• 16: B. Rau, "Iterative modulo scheduling." International Journal of Parallel Programming, vol.24, pp.3-64, Feb. 1996.
• 17: Alex Peleg , Uri Weiser, MMX Technology Extension to the Intel Architecture, IEEE Micro, v.16 n.4, p.42-50, August 1996 [doi>10.1109/40.526924]
• 18: S. P. Amarasinghe, et. al., "The SUIF compiler for scalable parallel machines." Proceedings of the Seventh SIAM Conference on Parallel Processing for Scientific Computing, February 1995.
• 19: LSI Logic Corporation, "LS401Z DSP," technical note, http://www.zsp.com/pdf/LSI4Ol.pdf, 1999.

INDEX TERMS

Primary Classification:
  J. Computer Applications

Additional Classification:
  B. Hardware
  B.1 CONTROL STRUCTURES AND MICROPROGRAMMING

  C. Computer Systems Organization

  D. Software
  D.3 PROGRAMMING LANGUAGES

  I. Computing Methodologies
  I.5 PATTERN RECOGNITION
      I.5.4 Applications
          Subjects: Signal processing

General Terms:
Design, Performance, Theory