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Influence of compiler optimizations on system power
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 37th Annual Design Automation Conference table of contents
Los Angeles, California, United States
Pages: 304 - 307  
Year of Publication: 2000
ISBN:1-58113-187-9
Authors
M. Kandemir  Microsystems Design Lab, The Pennsylvania State University, University Park, PA
N. Vijaykrishnan  Microsystems Design Lab, The Pennsylvania State University, University Park, PA
M. J. Irwin  Microsystems Design Lab, The Pennsylvania State University, University Park, PA
W. Ye  Microsystems Design Lab, The Pennsylvania State University, University Park, PA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 8,   Downloads (12 Months): 37,   Citation Count: 41
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ABSTRACT

High-level compiler optimizations ha ve been widely used to ac hiev e speedups on array-based codes. Su ch optimizations are becoming increasingly important in embedded signal processing and multimedia systems. The focus of these optimizations has traditionally been on improving performance. Ho w ev er, energy constraints are of critical importance in battery-operated embedded devices. In this paper, w e presen t an experimental evaluation of several state-of-the-art compiler optimizations on energy consumption, considering both the processor core (datapath) and memory system. This is in contrast to many of the previous works that ha ve considered them in isolation.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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D. Burger, T. Austin, and S. Bennett. Evaluating future microprocessors: the SimpleScalar tool set. Technical Report CS-TR-96-103, Computer Science Dept., University of Wisconsin, Madison, July 1996.
 
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F. Catthoor, F. Franssen, S. Wuytack, L. Nachtergaele, and H. DeMan. Global communication and memory optimizing transformations for low power signal processing systems. In Proc. the IEEE Workshop on VLSI Signal Processing, pages 178-187, 1994.
 
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A. Chandrakasan et.al., Optimizing power using transformations, IEEE Transactions on CAD, TCAD-14(1):12-31, Jan. 1995.
 
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CITED BY  41

Collaborative Colleagues:
M. Kandemir: colleagues
N. Vijaykrishnan: colleagues
M. J. Irwin: colleagues
W. Ye: colleagues