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ABSTRACT
This paper presents a method for general reduced order analysis of linear circuits with a large number of independent sources. This type of circuit is used to model the power grid in power supply noise analysis for example. The large size of the linear circuit model renders circuit simulation inefficient. The large number of independent sources makes conventional multi-port model reduction ineffective. In order to address these problems, this paper proposes an extended Krylov subspace method which constructs a transformation matrix based on the dynamics of the circuit as well as the source excitations, thus avoiding the multi-port problem of model reduction. The transformation matrix is then used to reduce the given circuit to a smaller circuit model, which allows for more efficient analysis.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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1
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H.H. Chen and J. S. Neely, "Interconnect and circuit modeling techniques for full chip power supply noise analysis," IEEE Trans. Compon. Packag. Manuf Technol. B, Adv. Packag., Vol.21, pp. 209-15, Aug. 1998.
|
| |
2
|
L. Pillage and R. A. Rohrer, "Asymptotic Waveform Evaluation for timing analysis", IEEE Trans. on Computer-aided design, vol. 9, pp. 352-366, April, 1990.
|
| |
3
|
P. Feldmann and R. W. Freund, "Efficient Linear Circuit Analysis by Pad6 Approximation via the Lanczos Process," IEEE Trans. Computer- Aided Design, vol. 14, pp. 639-649, May 1995.
|
| |
4
|
A. Odabasioglu, M. Celik, and L. T. Pileggi, "PRIMA: passive reduced order interconnect macromodeling algorithm," IEEE Trans. Computer- Aided Design, vol. 17, pp. 645-654, August 1998.
|
 |
5
|
Abhijit Dharchoudhury , Rajendran Panda , David Blaauw , Ravi Vaidyanathan , Bogdan Tutuianu , David Bearden, Design and analysis of power distribution networks in PowerPC microprocessors, Proceedings of the 35th annual conference on Design automation, p.738-743, June 15-19, 1998, San Francisco, California, United States
[doi> 10.1145/277044.277229]
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6
|
J.C. Shah, A. A. Younis, S. S. Sapatnekar, and M. M. Hassoun, "An algorithm for simulating power/ground networks using Pade approximants and its symbolic implementation ," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., Vol.45, pp. 1372-82, Oct. 1998
|
| |
7
|
E. Chiprout and T. Nguyen, "Power analysis of large interconnect grids withmultiple sources using model reduction", European Conference on Circuit Theory and Design, Stressa, Italy, Sept. 1999.
|
| |
8
|
J.Wang, T, Nuyen, "Extended Krylov Subspace Mehtod for power grid analysis",ERL Memorandum 2000.
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CITED BY 19
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Shiyou Zhao , Kaushik Roy , Cheng-Kok Koh, Decoupling capacitance allocation for power supply noise suppression, Proceedings of the 2001 international symposium on Physical design, p.66-71, April 01-04, 2001, Sonoma, California, United States
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Jin Shi , Yici Cai , Sheldon X.-D. Tan , Xianlong Hong, High accurate pattern based precondition method for extremely large power/ground grid analysis, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
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Yici Cai , Zhu Pan , Shelton X-D Tan , Xianlong Hong , Wenting Hou , Lifeng Wu, Relaxed hierarchical power/ground grid analysis, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
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Yahong Cao , Yu-Min Lee , Tsung-Hao Chen , Charlie Chung-Ping Chen, HiPRIME:: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
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Xiaoji Ye , Peng Li , Min Zhao , Rajendran Panda , Jiang Hu, Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
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Boyuan Yan , Lingfei Zhou , Sheldon X.-D. Tan , Jie Chen , Bruce McGaughy, DeMOR: decentralized model order reduction of linear networks with massive ports, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
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Pu Liu , Sheldon X.-D. Tan , Wei Wu , Murli Tirumala, FEKIS: a fast architecture-level thermal analyzer for online thermal regulation, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA
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Yici Cai , Jin Shi , Zhu Pan , Xianlong Hong , Sheldon X. -D. Tan, Large scale P/G grid transient simulation using hierarchical relaxed approach, Integration, the VLSI Journal, v.41 n.1, p.153-160, January, 2008
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Ning Mi , Sheldon X.-D. Tan , Pu Liu , Jian Cui , Yici Cai , Xianlong Hong, Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
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