A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance

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A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 37th Annual Design Automation Conference table of contents

Los Angeles, California, United States

Pages: 172 - 175

Year of Publication: 2000

ISBN:1-58113-187-9

Authors

Vikas Mehrotra	Massachusetts Institute of Technology, Cambridge, MA
Shiou Lin Sam	Massachusetts Institute of Technology, Cambridge, MA
Duane Boning	Massachusetts Institute of Technology, Cambridge, MA
Anantha Chandrakasan	Massachusetts Institute of Technology, Cambridge, MA
Rakesh Vallishayee	PDF Solutions, San Jose, CA
Sani Nassif	IBM, Austin, TX

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems

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ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 15, Downloads (12 Months): 46, Citation Count: 23

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ABSTRACT

We present a methodology to study the impact of spatial pattern dependent variation on circuit performance and implement the technique in a CAD framework. We investigate the effects of interconnect CMP and poly CD device variation on interconnect delay and clock skew in both aluminum and copper interconnect technology. Our results indicate that interconnect CMP variation strongly affects interconnect delay, while poly CD variation has a large impact on clock skew in a 1 GHz design. Given this circuit impact, CAD tools in the future must account for such systematic within-die variations.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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