Impact of interconnect variations on the clock skew of a gigahertz microprocessor

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Impact of interconnect variations on the clock skew of a gigahertz microprocessor

Full text

Pdf (74 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 37th Annual Design Automation Conference table of contents

Los Angeles, California, United States

Pages: 168 - 171

Year of Publication: 2000

ISBN:1-58113-187-9

Authors

Ying Liu	Department of Electrical and Computer Engineering, Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, PA
Sani R. Nassif	IBM Austin Research Lab, 11400 Burnet Road, Austin, TX
Lawrence T. Pileggi	Department of Electrical and Computer Engineering, Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, PA
Andrzej J. Strojwas	Department of Electrical and Computer Engineering, Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, PA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 56, Citation Count: 30

Additional Information:

abstract references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/337292.337365 What is a DOI?

ABSTRACT

Due to the large die sizes and tight relative clock skew margins, the impact of interconnect manufacturing variations on the clock skew in today's gigahertz microprocessors can no longer be ignored. Unlike manufacturing variations in the devices, the impact of the interconnect manufacturing variations on IC timing performance cannot be captured by worst/best case corner point methods. Thus it is difficult to estimate the clock skew variability due to interconnect variations. In this paper we analyze the timing impact of several key statistically independent interconnect variations in a context-dependent manner by applying a previously reported interconnect variational order-reduction technique. The results show that the interconnect variations can cause up to 25% clock skew variability in a modern microprocessor design.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Boning, D.S. and J.E. Chung, "Statistical metrology - measurement and modeling of variation for advanced process development and design rule generation", Proc. 1998 Int. Conf. on Characterization. and Metrology for ULSI Technology, March 1998.
	2	Hofstee, E el al, "A 1 GHz single-issue 64b PowerPC processor", Technical digest of lEEE Intl. Solid-State Circuit Conference(ISSCC), 2000.
	3	Ying Liu , Lawrence T. Pileggi , Andrzej J. Strojwas, Model order-reduction of RC(L) interconnect including variational analysis, Proceedings of the 36th ACM/IEEE conference on Design automation, p.201-206, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309914]
	4	Mehrotra, V., S. Nassif, D. Boning and J. Chung, "Modeling the effects of manufacturing variation on high-speed microprocessor interconnect performance", Proc. IEDM, 1998.
	5	Satyamurthy Pullela , Noel Menezes , Lawrence T. Pillage, Reliable non-zero skew clock trees using wire width optimization, Proceedings of the 30th international conference on Design automation, p.165-170, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164653]
	6	Sakurai, T. and K. Tamaru, "Simple formulas for two- and three-dimensional capacitances", IEEE Trans. Electron Devices, vol. ED-30, February 1983.
	7	Stine, B.E. et al, "The physical and electrical effects of metal fill patterning practices for oxide chemical mechanical polishing processes", IEEE Tran. Electron Devices, vol. 45, No. 3, March 1998.

CITED BY 30

	Blaise Gassend , Dwaine Clarke , Marten van Dijk , Srinivas Devadas, Delay-based circuit authentication and applications, Proceedings of the 2003 ACM symposium on Applied computing, March 09-12, 2003, Melbourne, Florida
	Kanak Agarwal , Dennis Sylvester , David Blaauw , Frank Liu , Sani Nassif , Sarma Vrudhula, Variational delay metrics for interconnect timing analysis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Anand Rajaram , Jiang Hu , Rabi Mahapatra, Reducing clock skew variability via cross links, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Makoto Mori , Hongyu Chen , Bo Yao , Chung-Kuan Cheng, A multiple level network approach for clock skew minimization with process variations, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.263-268, January 27-30, 2004, Yokohama, Japan
	James D. Ma , Rob A. Rutenbar, Fast interval-valued statistical interconnect modeling and reduction, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA
	Wai-Ching Douglas Lam , Cheng-Kok Koh, Process variation robust clock tree routing, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Ganesh Venkataraman , C. N. Sze , Jiang Hu, Skew scheduling and clock routing for improved tolerance to process variations, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Uday Padmanabhan , Janet M. Wang , Jiang Hu, Statistical clock tree routing for robustness to process variations, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
	Frank Huebbers , Ali Dasdan , Yehea Ismail, Computation of accurate interconnect process parameter values for performance corners under process variations, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Subodh M. Reddy , Gustavo R. Wilke , Rajeev Murgai, Analyzing timing uncertainty in mesh-based clock architectures, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Hanif Fatemi , Soroush Abbaspour , Massoud Pedram , Amir H. Ajami , Emre Tuncer, SACI: statistical static timing analysis of coupled interconnects, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	Xu Zhang , Xiaohong Jiang , Susumu Horiguchi, A non-orthogonal clock distribution network and its performance evaluation in presence of process variations and inductive effects, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	Takayuki Fukuoka , Akira Tsuchiya , Hidetoshi Onodera, Worst-case delay analysis considering the variability of transistors and interconnects, Proceedings of the 2007 international symposium on Physical design, March 18-21, 2007, Austin, Texas, USA
	Ganesh Venkataraman , Zhuo Feng , Jiang Hu , Peng Li, Combinatorial algorithms for fast clock mesh optimization, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	I-Jye Lin , Tsui-Yee Ling , Yao-Wen Chang, Statistical circuit optimization considering device andinterconnect process variations, Proceedings of the 2007 international workshop on System level interconnect prediction, March 17-18, 2007, Austin, Texas, USA
	Shiho Hagiwara , Takumi Uezono , Takashi Sato , Kazuya Masu, Improvement of power distribution network using correlation-based regression analysis, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	Dennis Sylvester , Kanak Agarwal , Saumil Shah, Invited paper: Variability in nanometer CMOS: Impact, analysis, and minimization, Integration, the VLSI Journal, v.41 n.3, p.319-339, May, 2008
	Ganesh Venkataraman , Jiang Hu , Frank Liu, Integrated placement and skew optimization for rotary clocking, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.2, p.149-158, February 2007
	J. D. Ma , R. A. Rutenbar, Interval-valued reduced order statistical interconnect modeling, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.460-467, November 07-11, 2004
	Basel Halak , Santosh Shedabale , Hiran Ramakrishnan , Alex Yakovlev , Gordon Russell, The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk, Proceedings of the 2008 international workshop on System level interconnect prediction, April 05-08, 2008, Newcastle, United Kingdom
	W.-C. D. Lam , J. Jam , C.-K. Koh , V. Balakrishnan , Y. Chen, Statistical based link insertion for robust clock network design, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.588-591, November 06-10, 2005, San Jose, CA
	Usha Narasimha , Binu Abraham , Nagaraj NS, Statistical Analysis of Capacitance Coupling Effects on Delay and Noise, Proceedings of the 7th International Symposium on Quality Electronic Design, p.795-800, March 27-29, 2006
	Hongliang Chang , Sachin S. Sapatnekar, Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.621, November 09-13, 2003
	Anand Rajaram , Bing Lu , Wei Guo , Rabi Mahapatra , Jiang Hu, Analytical Bound for Unwanted Clock Skew due to Wire Width Variation, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.401, November 09-13, 2003
	Aseem Agarwal , David Blaauw , Vladimir Zolotov, Statistical Clock Skew Analysis Considering Intra-Die Process Variations, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.914, November 09-13, 2003
	Frank Huebbers , Ali Dasdan , Yehea Ismail, Multi-layer interconnect performance corners for variation-aware timing analysis, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	I-Jye Lin , Yao-Wen Chang, An efficient algorithm for statistical circuit optimization using Lagrangian relaxation, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Won-Young Jung , Hyungon Kim , Yong-Ju Kim , Jae-Kyung Wee, Novel Method of Interconnect Worstcase Establishment with Statistically-Based Approaches, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E91-A n.4, p.1177-1184, April 2008
	Hai Wang , Hao Yu , Sheldon X.-D. Tan, Fast analysis of nontree-clock network considering environmental uncertainty by parameterized and incremental macromodeling, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan
	Shiho Hagiwara , Takumi Uezono , Takashi Sato , Kazuya Masu, Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E91-A n.4, p.951-956, April 2008