Test challenges for deep sub-micron technologies

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Test challenges for deep sub-micron technologies

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 37th Annual Design Automation Conference table of contents

Los Angeles, California, United States

Pages: 142 - 149

Year of Publication: 2000

ISBN:1-58113-187-9

Authors

Kwang-Ting Chueng
Sujit Dey
Mike Rodgers
Kaushik Roy

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Citation Count: 14

Additional Information:

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ABSTRACT

The use of deep submicron process technologies presents several new challenges in the area of manufacturing test. While a significant body of work has been devoted to identifying and investigating design challenges in nanometer technologies, the impact on test strategies and methodologies is still not well understood. This paper highlights the challenges to current test methodologies arising from technology driven trends, and will present an overview of emerging techniques that address deep submicron test challenges.

CITED BY 14

	Jing-Jia Liou , Li-C. Wang , Angela Krstic , Kwang-Ting Cheng, Experience in critical path selection for deep sub-micron delay test and timing validation, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	A. Krstic , L.-C. Wang , K.-T. Cheng , J.-J. Liou , T. M. Mak, Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Jing-Jia Liou , Li-C. Wang , Kwang-Ting Cheng, On theoretical and practical considerations of path selection for delay fault testing, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.94-100, November 10-14, 2002, San Jose, California
	Katarzyna Radecka , Zeljko Zilic, Design Verification by Test Vectors and Arithmetic Transform Universal Test Set, IEEE Transactions on Computers, v.53 n.5, p.628-640, May 2004
	Cecilia Metra , Stefano Di Francescantonio , T. M. Mak, Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing, IEEE Transactions on Computers, v.53 n.5, p.531-546, May 2004
	Huawei Li , Xiaowei Li, Selection of Crosstalk-Induced Faults in Enhanced Delay Test, Journal of Electronic Testing: Theory and Applications, v.21 n.2, p.181-195, April 2005
	Seiji Kajihara , Masayasu Fukunaga , Xiaoqing Wen , Toshiyuki Maeda , Shuji Hamada , Yasuo Sato, Path delay test compaction with process variation tolerance, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Masayasu Fukunaga , Seiji Kajihara , Xiaoqing Wen , Toshiyuki Maeda , Shuji Hamada , Yasuo Sato, A dynamic test compaction procedure for high-quality path delay testing, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Seiji Kajihara , Shohei Morishima , Masahiro Yamamoto , Xiaoqing Wen , Masayasu Fukunaga , Kazumi Hatayama , Takashi Aikyo, Estimation of delay test quality and its application to test generation, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Vikram Iyengar , Jinjun Xiong , Subbayyan Venkatesan , Vladimir Zolotov , David Lackey , Peter Habitz , Chandu Visweswariah, Variation-aware performance verification using at-speed structural test and statistical timing, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Katherine Shu-Min Li , Chung-Len Lee , Chauchin Su , Jwu E. Chen, IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection, Journal of Electronic Testing: Theory and Applications, v.23 n.4, p.341-355, August 2007
	Angela Krstic , Li-C. Wang , Kwang-Ting Cheng , Jing-Jia Liou , Magdy S. Abadir, Delay Defect Diagnosis Based Upon Statistical Timing Models " The First Step, Proceedings of the conference on Design, Automation and Test in Europe, p.10328, March 03-07, 2003
	Mango , C.-T. Chao , Li-C. Wang , Kwang-Ting Cheng, Pattern Selection for Testing of Deep Sub-Micron Timing Defects, Proceedings of the conference on Design, automation and test in Europe, p.2160, February 16-20, 2004
	Kaushik Roy , T. M. Mak , Kwang-Ting (Tim) Cheng, Test Consideration for Nanometer-Scale CMOS Circuits, IEEE Design & Test, v.23 n.2, p.128-136, March 2006