System chip test: how will it impact your design?

ABSTRACT

A major challenge in realizing core-based system chips is the adoption and design-in of adequate test and diagnosis strategies. This tutorial paper discusses the specific challenges that come with testing deeply embedded reusable cores supplied by diverse providers, who often use different hardware description levels and mixed technologies. The paper describes a general test access architecture for embedded cores, and covers the current standardization efforts in this domain. In addition, we give an overview of the emerging EDA developments in SOC test, and illustrate the current industrial practices by means of two case studies.

REFERENCES

• 1: Rajesh K. Gupta , Yervant Zorian, Introducing Core-Based System Design, IEEE Design & Test, v.14 n.4, p.15-25, October 1997 [doi>10.1109/54.632877]
• 2: IEEE Computer Society. IEEE Standard Test Access Port and Boundary-Scan Architecture - IEEE Std. 1149.1-1990. IEEE, New York, 1990.
• 3: Erik Jan Marinissen and Yervant Zorian. Challenges in Testing Core- Based System ICs. IEEE Communications Magazine, 37(6):104-109, June 1999.
• 4: Yervant Zorian , Erik Jan Marinissen , Sujit Dey, Testing embedded-core based system chips, Proceedings of the 1998 IEEE International Test Conference, p.130, October 18-22, 1998
• 5: Erik Jan Marinissen , Robert G. J. Arendsen , Gerard Bos , Hans Dingemanse , Maurice Lousberg , Clemens Wouters, A structured and scalable mechanism for test access to embedded reusable cores, Proceedings of the 1998 IEEE International Test Conference, p.284-293, October 18-22, 1998
• 6: Prab Varma , Sandeep Bhatia, A structured test re-use methodology for core-based system chips, Proceedings of the 1998 IEEE International Test Conference, p.294-302, October 18-22, 1998
• 7: Lee Whetsel, Addressable Test Ports An Approach to Testing Embedded Cores, Proceedings of the 1999 IEEE International Test Conference, p.1055, September 28-30, 1999
• 8: Erik Jan Marinissen , Yervant Zorian , Rohit Kapur , Tony Taylor , Lee Whetsel, Towards a Standard for Embedded Core Test: An Example, Proceedings of the 1999 IEEE International Test Conference, p.616, September 28-30, 1999
• 9: IEEE P1500 Web Site. http://grouper.ieee.org/groups/1500/.
• 10: Anthony Taylor , Gregory A. Maston, Standard Test Interface Language (STIL): A New Language for Patterns and Waveforms, Proceedings of the IEEE International Test Conference on Test and Design Validity, p.565-570, October 20-25, 1996
• 11: IEEE Computer Society. IEEE Standard Test Interface Language (STIL) for Digital Test Vector Data - IEEE Std. 1450-1999. IEEE, New York, 1999.
• 12: IEEE 1450 Web Site. http://grouper.ieee.org/groups/1450/.
• 13: Joep Aerts , Erik Jan Marinissen, Scan chain design for test time reduction in core-based ICs, Proceedings of the 1998 IEEE International Test Conference, p.448-457, October 18-22, 1998
• 14: Krishnendu Chakrabarty, Design of System-on-a-Chip Test Access Architectures using Integer Linear Programming, Proceedings of the 18th IEEE VLSI Test Symposium (VTS'00), p.127, April 30-May 04, 2000
• 15: Krishnendu Chakrabarty, Design of system-on-a-chip test access architectures under place-and-route and power constraints, Proceedings of the 37th conference on Design automation, p.432-437, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337531]
• 16: Erik Jan Marinissen, Krijn Kuiper, and Clemens Wouters. Test Protocol Expansion in Hierarchical Macro Testing. In Proceedings IEEE European Test Conference (ETC), pages 28-36, Rotterdam, The Netherlands, April 1993. IEEE Computer Society Press.
• 17: Erik Jan Marinissen , Maurice Lousberg, The Role of Test Protocols in Testing Embedded-Core-Based System ICs, Proceedings of the 1999 IEEE European Test Workshop, p.70, September 24-27, 1999
• 18: Erik Jan Marinissen and Joep Aerts. Test Protocol Scheduling for Embedded-Core Based System ICs. In Digest of Papers of lEEE International Workshop on Testing Embedded Core-Based Systems (TECS), pages 5.3-1-9, Washington, DC, October 1998.
• 19: Krishnendu Chakrabarty, Test scheduling for core-based systems, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.391-394, November 07-11, 1999, San Jose, California, United States
• 20: Yervant Zorian. A Distributed BIST Control Scheme for Complex VLSI Devices. In Proceedings IEEE VLSI Test Symposium (VTS), pages 6-11, Princeton, NJ, April 1993. IEEE Computer Society Press.
• 21: Sujit Dey, Erik Jan Marinissen, and Yervant Zorian. Testing System Chips: Methodologies and Experiences. Integrated System Design, Vol. 1 l(No. 123):36-48, September 1999.
• 22: Sobhan Mukherji, Loc Nguyen, Dwayne Burek, and Steve Baird. IP/VC-Based Test Methodology (Part-l): A Case Study. InDigest of Papets of lEEE International Workshop on Testing Embedded Core-Based Systems (TECS), pages 1.2-1-9, Washington, DC, October 1998.
• 23: Yervant Zorian , Erik Jan Marinissen , Sujit Dey, Testing embedded-core based system chips, Proceedings of the 1998 IEEE International Test Conference, p.130, October 18-22, 1998

INDEX TERMS

Primary Classification:
  J. Computer Applications

Additional Classification:
  A. General Literature

  B. Hardware
  B.8 Performance and Reliability

  K. Computing Milieux
  K.1 THE COMPUTER INDUSTRY
      Subjects: Standards

General Terms:
Design, Performance, Reliability, Standardization, Theory