| BDS: a BDD-based logic optimization system |
| Full text |
Pdf
(123 KB)
|
| Source
|
Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 37th Annual Design Automation Conference
table of contents
Los Angeles, California, United States
Pages: 92 - 97
Year of Publication: 2000
ISBN:1-58113-187-9
|
|
Authors
|
|
Congguang Yang
|
Dept. of Electrical & Computer Engineering, University of Massachusetts, Amherst, MA
|
|
Maciej Ciesielski
|
Dept. of Electrical & Computer Engineering, University of Massachusetts, Amherst, MA
|
|
Vigyan Singhal
|
Tempus Fugit, Inc., Albany, CA
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 14, Downloads (12 Months): 38, Citation Count: 7
|
|
|
ABSTRACT
This paper describes a new BDD-based logic optimization system, BDS. It is based on a recently developed theory for BDD-based logic decomposition, which supports both algebraic and Boolean factorization. New techniques, which are crucial to the manipulation of BDDs in a partitioned Boolean network environment, are described in detail. The experimental results show that BDS has a capability to handle very large circuits. It offers a superior runtime advantage over SIS, with comparable results in terms of circuit area and often improved delay.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
 |
1
|
|
| |
2
|
S.B. Akers, "Functional Testing with Binary Decision Diagrams," in Eighth Annual Conference on Fault- Tolerant Computing, 1978, pp. 75-82.
|
| |
3
|
|
 |
4
|
Karl S. Brace , Richard L. Rudell , Randal E. Bryant, Efficient implementation of a BDD package, Proceedings of the 27th ACM/IEEE conference on Design automation, p.40-45, June 24-27, 1990, Orlando, Florida, United States
[doi> 10.1145/123186.123222]
|
| |
5
|
Yung-Te Lai, Kuo-Rueih Pan, and Massoud Pedram, "OBDD-Based Function Decomposition: Algorithms and Implementattion," IEEE Trans. on CAD, vol. 15, no. 8, pp. 977-990, August 1996.
|
| |
6
|
Shih-Chieh Chang, M. Marek-Sadowska, and T. Hwang, "Technology Mapping for TLU FPGA's Based on Decomposition of Binary Decision Diagrams," IEEE Trans. on CAD, vol. 15, no. 10, pp. 1226-1235, October 1996.
|
| |
7
|
|
| |
8
|
K. Yano, Y. Sasaki, K. Rikino, and K. Seki, "Top-Down Pass Transistor Logic Design," IEEE J. Solid-State Circuits, vol. 31, no. 6, pp. 792~803, June 1996.
|
| |
9
|
P. Buch, A. Narayan, R. Newton, and A. Sangiovanni-Vincentelli, "On Synthesizing Pass Transistor Logic," in Intl. Workshop on Logic Synthesis, 1997.
|
| |
10
|
|
| |
11
|
|
| |
12
|
|
| |
13
|
Ted Stanion and Carl Sechen, "Boolean Division and Factorization Using Binary Decision Diagrams," IEEE Trans. on CAD, vol. 13, no. 9, pp. 1179-1184, September 1994.
|
| |
14
|
S. Minato, "Fast Factorization Method for Implicit Cube Set Representation," IEEE Trans. on CAD, vol. 15, no. 4, pp. 377-384, April 1996.
|
 |
15
|
|
| |
16
|
S. Yamashita, K. Yano, Y. Sasaki, Y. Akita, H Chikata, K. Rikino, and K Seki, "Pass-Transistor/CMOS Collaborated Logic: The Best of Both Worlds," in Symposium on VLSI Circuits Digest of Technical Papers, 1997, pp. 31-32.
|
| |
17
|
C. Yang and M. Ciesielski, "Synthesis for Mixed CMOS/PTL Logic: Preliminary Results," in International Workshop on Logic Synthesis, 1999.
|
| |
18
|
|
| |
19
|
E. Sentovich et al., "SIS: A System for Sequential Circuit Synthesis," Tech. Rep. UCB/ERL M92/41, ERL, Dept. of EECS, Univ. of California, Berkeley., 1992.
|
| |
20
|
|
|