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BDS: a BDD-based logic optimization system
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 37th Annual Design Automation Conference table of contents
Los Angeles, California, United States
Pages: 92 - 97  
Year of Publication: 2000
ISBN:1-58113-187-9
Authors
Congguang Yang  Dept. of Electrical & Computer Engineering, University of Massachusetts, Amherst, MA
Maciej Ciesielski  Dept. of Electrical & Computer Engineering, University of Massachusetts, Amherst, MA
Vigyan Singhal  Tempus Fugit, Inc., Albany, CA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 14,   Downloads (12 Months): 38,   Citation Count: 7
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ABSTRACT

This paper describes a new BDD-based logic optimization system, BDS. It is based on a recently developed theory for BDD-based logic decomposition, which supports both algebraic and Boolean factorization. New techniques, which are crucial to the manipulation of BDDs in a partitioned Boolean network environment, are described in detail. The experimental results show that BDS has a capability to handle very large circuits. It offers a superior runtime advantage over SIS, with comparable results in terms of circuit area and often improved delay.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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C. Yang and M. Ciesielski, "Synthesis for Mixed CMOS/PTL Logic: Preliminary Results," in International Workshop on Logic Synthesis, 1999.
 
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E. Sentovich et al., "SIS: A System for Sequential Circuit Synthesis," Tech. Rep. UCB/ERL M92/41, ERL, Dept. of EECS, Univ. of California, Berkeley., 1992.
 
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Collaborative Colleagues:
Congguang Yang: colleagues
Maciej Ciesielski: colleagues
Vigyan Singhal: colleagues