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Annual ACM Symposium on Theory of Computing
archive
Proceedings of the thirty-second annual ACM symposium on Theory of computing
table of contents
Portland, Oregon, United States
Pages: 73 - 79
Year of Publication: 2000
ISBN:1-58113-184-4
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Authors
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Valentine Kabanets
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Department of Computer Science, University of Toronto, Toronto, Canada
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Jin-Yi Cai
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Department of Computer Science, State University of New York at Buffalo, Buffalo, NY
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| Bibliometrics |
Downloads (6 Weeks): 6, Downloads (12 Months): 47, Citation Count: 2
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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O. Goldreich and D. Zuckerman. Another proof that BPPCPH (and more). Electronic Colloquium on Computational Complexity, TR97-045, 1997.
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R. Kannan. Circuit-size lower bounds and nonreducibility to sparse sets. Information and Control, 55'40-56, 1982.
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C. Lautemann. BPP and the polynomial time hierarchy. Information Processing Letters, 17:215-218, 1983.
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H. Lenstra Jr. and C. Pomerance. A rigorous time bound for factoring integers. Journal of the American Mathematical Society, 5(3):483-516, 1992.
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O. Lupanov. A method of circuit synthesis. Izvestiya VUZ, Radiofizika, 1(1):120-140, 1959. (in Russian).
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O. Lupanov. On the synthesis of certain classes of control systems. In Problemy Kibernetiki 10, pages 63-97. Fizmatgiz, Moscow, 1963. (in Russian).
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W. Masek. Some NP-complete set covering problems. Manuscript, 1979.
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P. B. Miltersen, N. Vinodchadran, and O. Watanabe. Super-polynomial versus half-exponential circuit size in the exponential hierarchy. In T. Asano, H. Imai, D. Lee, S. Nakano, and T. Tokuyama, editors, Proceedings of the Fifth Annual International Conference on Computing and Combinatorics, volume 1627 of Lecture Notes in Computer Science, pages 210-220. Springer Verlag, 1999. (COCOON'99).
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J. Pollard. Theorems on factorization and primality testing. Proceedings of the Cambridge Philosophical Society, 76:521-528, 1974.
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C. Shannon. The synthesis of two-terminal switching circuits. Bell Systems Technical Journal, 28(1):59-98, 1949.
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V. Strassen. Einige Resultate /iber Berechnungskomplexit~it. Jahresberichte der DMV, 78:1-8, 1976.
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B. Trakhtenbrot. A survey of Russian approaches to perebor (brute-force search) algorithms. Annals of the History of Computing, 6(4):384-400, 1984.
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S. Yablonski. The algorithmic difficulties of synthesizing minimal switching circuits. In Problemy Kibernetiki 2, pages 75-121. Fizmatgiz, Moscow, 1959. English translation in Problems of Cybernetics II.
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S. Yablonski. On the impossibility of eliminating perebor in solving some problems of circuit theory. Doklady Akademii Nauk SSSR, 124(1):44-47, 1959. English translation in Soviet Mathematics Doklady.
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