ACM Home Page
Please provide us with feedback. Feedback
Automated cache optimizations using CME driven diagnosis
Full text PdfPdf (1.11 MB)
Source International Conference on Supercomputing archive
Proceedings of the 14th international conference on Supercomputing table of contents
Santa Fe, New Mexico, United States
Pages: 316 - 326  
Year of Publication: 2000
ISBN:1-58113-270-0
Authors
Somnath Ghosh  Department of Electrical Engineering, Princeton University
Margaret Martonosi  Department of Electrical Engineering, Princeton University
Sharad Malik  Department of Electrical Engineering, Princeton University
Sponsor
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 1,   Downloads (12 Months): 15,   Citation Count: 4
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/335231.335262
What is a DOI?

ABSTRACT

Demonstrating our framework on a collection of scientific loop nests, we were able to reduce an average of 84% of cache misses in the optimizable loop nests. This work lays the groundwork for handling a wide range of optimizations through further study of solution patterns in the CME solution table.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
 
2
 
3
 
4
5
6
 
7
 
8
9
10
 
11
12
 
13
 
14
M. Lain, E. E. Rothberg, and M. E. Wolf. The cache performance of blocked algorithms. In Proceedings of the 4th International Conference on Architectural Support for Programming Languages and Operating Systems, Apr. 1991.
 
15
16
17
18
 
19
M. F. P. O'Boyle and P. M. W. Knijnenburg. Efficient parallelisation using combined loop and data transformations. In Proceedings of the 8th International Workshop on Compilers for Parallel Computers, Jan. 2000.
20
21
 
22
X. Veto, J. Llosa, A. Gonzalez, and C. Cinraneta. A fast implementation of Cache Miss Equations. In Proceedings of the 8th International Workshop on Compilers for Parallel Computers, Jan. 2000.
23
 
24
25


Collaborative Colleagues:
Somnath Ghosh: colleagues
Margaret Martonosi: colleagues
Sharad Malik: colleagues