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System-level power optimization: techniques and tools
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Source ACM Transactions on Design Automation of Electronic Systems (TODAES) archive
Volume 5 ,  Issue 2  (April 2000) table of contents
Pages: 115 - 192  
Year of Publication: 2000
ISSN:1084-4309
Authors
Luca Benini  Univ. di Bologna
Giovanni de Micheli  Stanford Univ.
Publisher
ACM  New York, NY, USA
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ABSTRACT

This tutorial surveys design methods for energy-efficient system-level design. We consider electronic sytems consisting of a hardware platform and software layers. We consider the three major constituents of hardware that consume energy, namely computation, communication, and storage units, and we review methods of reducing their energy consumption. We also study models for analyzing the energy cost of software, and methods for energy-efficient software design and compilation. This survery is organized around three main phases of a system design: conceptualization and modeling design and implementation, and runtime management. For each phase, we review recent techniques for energy-efficient design of both hardware and software.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
ADVANCED MICRO DEVICES, 1998. AM29SLxxx low-voltage flash memories.
 
2
ADVANCED RISC MACHINES LTD., 1996. ARM software development toolkit version 2.11.
 
3
AGRAWAL, P. 1998. Energy conservation design techniques for mobile wireless VLSI systems. In Proceedings of the Computer Society Workshop on VLSI System-Level Design (Apr.), 34-39.
 
4
5
 
6
 
7
BAMBOS, N. 1998. Toward power-sensitive network architectures in wireless communications. IEEE Personal Commun. 5, 3 (June), 50-58.
 
8
 
9
 
10
 
11
12
13
 
14
BENINI, L., BOGLIOLO, A., PALEOLOGO, G., AND DE MICHELI, G. 1999b. Policy optimization for dynamic power management. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 18, 6 (June), 813-833.
15
16
 
17
 
18
CATTHOOR, F., FRANSSEN, F., WUYTACK, S., NACHTERGAELE, L., AND DE MAN, H. 1994. Global communication and memory optimizing transformations for low power systems. In Proceedings of the International Workshop on Low Power Design, 203-208.
 
19
 
20
CATTHOOR, F., WUYTACK, S., DE GREEF, E., FRANSSEN, F., NACHTERGAELE, L., AND DE MAN, H. 1998b. System-level transformations for low-power data transfer and storage. In Low- Power CMOS Design, R. Chandrakasan and R. Brodersen, Eds. IEEE Press, Piscataway, NJ.
 
21
CHANDRAKASAN, A. P., POTKONJAK, M., MEHRA, R., RABAEY, J., AND BRODERSEN, R. 1995. Optimizing power using transformations. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 14, 1 (Jan.), 13-32.
 
22
 
23
 
24
 
25
26
27
 
28
29
 
30
 
31
DASGUPTA, A. AND KARRI, R. 1998. High-reliability, low-energy microarchitecture synthesis. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 17, 12 (Dec.), 1273-1280.
32
 
33
 
34
 
35
DE GREEF, E., CATTHOOR, F., AND DE MAN, H. 1998. Program transformation strategies for memory size and power reduction of pseudoregular multimedia subsystems. IEEE Trans. Circuits Syst. Video Technol. 8, 6 (Oct.), 719-733.
 
36
DE MICHELI, a. AND GUPTA, R. 1997. Hardware/sofware co-design. Proc. IEEE 95, 3 (Mar.), 349-365.
 
37
 
38
 
39
DOUGHERTY, W., PURSLEY, D., AND THOMAS, D. 1998. Instruction subsetting: Trading power for programmability. In Proceedings of the Computer Society Workshop on VLSI System-Level Design (Apr.), 42-47.
 
40
 
41
42
 
43
44
 
45
 
46
 
47
 
48
49
 
50
 
51
GOLDING, R., BOSH, P., AND WILKES, J. 1996. Idleness is not Sloth. Hewlett-Packard, Fort Collins, CO.
 
52
GONZALEZ, R. AND HOROWITZ, M. 1996. Energy dissipation in general purpose microprocessors. IEEE J. Solid-State Circuits 31, 9 (Sept.), 1277-1284.
 
53
GOOSSENS, G., PAULIN, P., VAN PRAET, J., LANNEER, D., GUERTS, W., KIFLI, A., AND LIEM, C. 1997.Embedded software in real-time signal processing systems: Design technologies. Proc. IEEE 85, 3 (Mar.), 436-454.
54
55
56
 
57
58
 
59
HARRIS ET AL., E. 1995. Technology directions for portable computers. Proc. IEEE 83, 4 (Apr.), 636-657.
 
60
61
62
63
64
 
65
 
66
67
68
 
69
 
70
 
71
INTEL. 1998. SA-1100 Microprocessor Technical Reference Manual. Intel Corp., Santa Clara, CA.
72
 
73
ISHIHARA, T. AND YASUURA, M. 1998. Power-Pro: Programmable power management architecture. In Proceedings of the on Asia and South Pacific Design Automation (Feb.), 321-322.
 
74
ITOH, K., SASAKI, K., AND NAKAGOME, Y. 1995. Trends in low-power RAM circuit technologies. Proc. IEEE 83, 4 (Apr.), 524-543.
 
75
 
76
JouPPI, N. AND WILTON, N. 1996. CACTI: An enhanced cache access and cycle time model. IEEE J. Solid-State Circuits 31, 5 (May), 677-688.
77
78
79
 
80
 
81
KARLIN, A., MANASSE, M., MCGEOCH, L., AND OWICKI, S. 1994. Competitive randomized algorithms for nonuniform problems. Algorithmica 11, 6 (June), 542-571.
82
 
83
84
 
85
KIROVSKI, D., LEE, C., POTKONJAK, M., AND MANGIONE-SMITH, W. 1998. Synthesis of power efficient systems-on-silicon. In Proceedings of the Conference on Asian and South Pacific Design Automation (Feb.), 557-562.
86
 
87
 
88
 
89
KRISHNAN, P., LONG, P., AND VITTER, g. 1995. Adaptive disk spindown via optimal rent-to-buy in probabilistic environments. In Proceedings of the 12th International Conference on Machine Learning (Lake Tahoe, CA), 322-330.
 
90
KULKARNI, C., CATTHOOR, F., AND DE MAN, H. 1998. Code transformations for low power caching in embedded multimedia processors. In Proceedings of the First Merged IPPS/ SPDP Symposium on Parallel and Distributed Processing (IPPS/SPDP '98, Mar.), 23-26.
 
91
92
 
93
 
94
LEE ET AL., W. 1997. A I-V programmable DSP for wireless communications. IEEE J. Solid-State Circuits 32, 11 (Nov.), 1766-1776.
 
95
LEE, E. AND SANGIOVANNI-VINCENTELLI, A. 1998. A framework for comparing models of computation. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 17, 12 (Dec.), 1217- 1229.
96
97
 
98
LIAO, S., DEVADAS, S., AND KEUTZER, K. 1998. Code density optimization for embedded DSP processors using data compression techniques. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 17, 7 (July), 601-608.
99
 
100
LIDSKY, D. AND RABAEY, J. 1994. Low-power design of memory intensive functions. In Proceedings of the IEEE Symposium on Low Power Electronics (Sept.), IEEE Computer Society Press, Los Alamitos, CA, 16-17.
 
101
 
102
LORCH, g. AND SMITH, A. 1998. Software strategies for portable computer energy management. IEEE Personal Commun. 5, 3 (June).
 
103
104
 
105
LUDWIG, J., NAWAB, H., AND CHANDRAKASAN, A. 1996. Low-power digital filtering using approximate processing. IEEE J. Solid-State Circuits 31, 3 (Mar.), 395-399.
 
106
MACII, E., PEDRAM, M., AND SOMENZI, F. 1998. High-level power modeling, estimation and optimization. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 17, 11 (Nov.), 1061- 1079.
107
 
108
 
109
 
110
MEHRA, R., GUERRA, L., AND RABAEY, J. 1997. A partitioning scheme for optimizing interconnect power. IEEE J. Solid-State Circuits 32, 3 (Mar.), 433-443.
 
111
112
 
113
MENDL, J. 1995. Low power microelectronics: Retrospect and prospect. Proc. IEEE 83, 4 (Apr.), 619-635.
 
114
MENG, T., GORDON, B., TSENG, E., AND HUNG, A. 1995. Portable video-on-demand in wireless communication. Proc. IEEE 83, 4 (Apr.), 659-690.
 
115
MICROSOFT AND TOSHIBA. 1996. Advanced configuration and power interface specification. Tech. Rep.
 
116
MICROSOFT. 1997. OnNow: the evolution of the PC platform. Microsoft Press, Redmond, WA.
117
 
118
 
119
 
120
MUTOH, S., SHIGEMATSU, S., MATSUYA, Y., FUKUDA, H., KANEKO, T., AND YAMADA, J. 1996. A I-V multithreshold-voltage CMOS digital signal processor for mobile phone applications. IEEE J. Solid-State Circuits 31, 11 (Nov.), 1795-1802.
 
121
 
122
NAMGOONG, W., YU, M., AND MENG, T. 1997. A high-efficiency variable-voltage CMOS dynamic DC-DC switching regulator. In Proceedings of the IEEE International Conference on Solid-State Circuits, IEEE Computer Society Press, Los Alamitos, CA, 380-381.
 
123
 
124
 
125
NISHITANI, T.1999.Low-power architectures for programmable multimedia processors.IEICE Trans. Fundam. Electron. Commun. Comput. Sci. E82-A, 2 (Feb.), 184-196.
 
126
127
128
 
129
130
131
 
132
POTKONJAK, M. AND RABAEY, M. 1999. Algorithm selection: A quantitative optimizationintensive approach. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 18, 5 (May), 524-532.
 
133
PUTERMAN, M. 1994. Finite Markov Decision Processes. John Wiley and Sons, Inc., New York, NY.
134
 
135
RABAEY, J. AND PEDRAM, M. 1996. Low Power Design Methodologies. Kluwer Academic, Dordrecht, Netherlands.
 
136
RAGHUNATHAN, A. AND JHA, N. 1997. SCALP: An iterative improvement-based low-power datapath synthesis algorithm. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 14, 11 (Nov.), 1260-1277.
 
137
 
138
RAGHUNATHAN, A., DEY, S., AND JHA, N. 1999. Register transfer level power optimization with emphasis on glitch analysis and reduction. IEEE Trans. Comput.-Aided Des. 18, 8 (Aug.), 1114-1131.
139
 
140
RAMPRASAD, S., SHANBHAG, N., AND HAJJ, I. 1998. Signal coding for low power: Fundamental limits and practical realizations. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), IEEE Computer Society Press, Los Alamitos, CA.
 
141
Ross, S. 1997. Introduction to Probability Models. Academic Press, Inc., New York, NY.
 
142
SACHA, J. AND IRWIN, M. 1998. Number representation for reducing switching capacitance in subband coding. In Proceedings of the International Conference on Acoustics, Speech and Signal Processing (May), 12-15.
 
143
SAIED, R. AND CHAKRABARTI, C. 1996. Scheduling for minimizing the number of memory accesses in low power applications. In VLSI Signal Processing 169-178.
 
144
 
145
146
147
148
149
 
150
SRATAKOS, A., SANDERS, S., AND BRODERSEN, R. 1994. A low-voltage CMOS DC-DC converter for a portable battery-operated system. In Proceedings of the IEEE Conference on Power Electronics Specialists, IEEE Computer Society Press, Los Alamitos, CA, 619-626.
 
151
152
 
153
 
154
 
155
STEMM, M. AND KATZ, R. 1997. Measuring and reducing energy consumption of network interfaces in hand-held devices. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. E80-B, 8 (Aug.), 1125-1131.
 
156
157
 
158
SUZUKI ET AL., K. 1997. A 300 MIPS/W RISC core processor with variable supply-voltage scheme in variable threshold-voltage CMOS. In Proceedings of the Conference on Custom Integrated Circuits (May), 112-118.
 
159
 
160
161
 
162
 
163
USAMI, K. AND IGARASHI ET AL., M. 1998. Automated low-power technique exploiting multiple supply voltages applied to a media processor. IEEE J. Solid-State Circuits 33, 3 (Mar.), 463-472.
164
 
165
 
166
VITTOZ, E. 1994. Low power microelectronics: Ways to approach the limits. In Proceedings of the International Conference on Solid-State Circuits (Jan.), 14-18.
 
167
WAN, M., ICHIKAWA, Y., LIDSKY, D., AND RABAEY, J. 1998. An energy conscious methodology for aarly design exploration of heterogeneous DSPs. In Proceedings of the Conference on Custom Integrated Circuits (May), 111-117.
 
168
 
169
WEISER, M., WELCH, B., DEMERS, A., AND SHENKER, S. 1994. Scheduling for reduced CPU energy. In Proceedings of the First USENIX Symposium on Operating Systems Design and Implementation (Monterey, CA, May), USENIX Assoc., Berkeley, CA, 13-23.
 
170
WINZKER, M. 1998. Low-power arithmetic for the processing of video signals. IEEE Trans. Very Large Scale Integr. Syst. 6, 3 (Sept.).
 
171
WOLF, W. 1994. Hardware-software co-design of embedded systems. Proc. IEEE 82, 7 (July 1994), 967-989.
 
172
WOLFE, A. 1996. Issues for low-power CAD tools: A system-level design study. J. Des. Autom. Embedded Syst. 1, 4, 315-332.
 
173
WUYTACK, S., CATTHOOR, F., AND DE MAN, H. 1997. Transforming set data types to power optimal data structures. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 15, 6 (June), 619-629.
 
174
175
176
 
177
ZHANG, Y., HU, X., AND CHEN, D. 1999. Low energy register allocation beyond basic blocks. In Proceedings of the International Symposium on Circuits and Systems (June), 290-293.
178

CITED BY  78

Collaborative Colleagues:
Luca Benini: colleagues
Giovanni de Micheli: colleagues