Frequency interleaving as a codesign scheduling paradigm

ABSTRACT

Frequency interleaving is introduced as a means of conceptualizing and co-scheduling hardware and software behaviors so that software models with conceptually unbounded state and execution time are resolved with hardware resources. The novel mechanisms that result in frequency interleaving are a shared memory foundation for all system modeling (from gates to software-intensive subsystems) and de-coupled, but interrelated time- and state-interleaved scheduling domains. The result for system modeling is greater accommodation of software as a configuration paradigm that loads system resources, a greater accommodation of shared memory modeling, and a greater representation of software schedulers as a system architectural abstraction. The results for system co-simulation are a lessening of the dependence on discrete event simulation as a means of merging physical and non-physical models of computation, and a lessening of the need to partition a system as computation and communication too early in the design. We include an example demonstrating its implementation.

REFERENCES

• 1: Felice Balarin , Massimiliano Chiodo , Paolo Giusto , Harry Hsieh , Attila Jurecska , Luciano Lavagno , Claudio Passerone , Alberto Sangiovanni-Vincentelli , Ellen Sentovich , Kei Suzuki , Bassam Tabbara, Hardware-software co-design of embedded systems: the POLIS approach, Kluwer Academic Publishers, Norwell, MA, 1997
• 2: Grady Booch , James Rumbaugh , Ivar Jacobson, The Unified Modeling Language user guide, Addison Wesley Longman Publishing Co., Inc., Redwood City, CA, 1999
• 3: Wan-Teh Chang , Soonhoi Ha , Edward A. Lee, Heterogeneous Simulation—Mixing Discrete-Event Models with Dataflow, Journal of VLSI Signal Processing Systems, v.15 n.1-2, p.127-144, Jan. 1997 [doi>10.1023/A:1007930622942]
• 4: Jean-Marc Daveau , Gilberto Marchioro , Ahmed Amine Jerraya, Hardware/software co-design of an ATM network interface card: a case study, Proceedings of the 6th international workshop on Hardware/software codesign, p.111-115, March 15-18, 1998, Seattle, Washington, United States
• 5: J. Davis II, M. Goel, C. Hylands, B. Kienhuis, E. Lee, et. al, "Overview of the Ptolemy Project," ERL Technical Report UCB/ERL No. M99/37, Dept. EECS, Berkeley. July 1999.
• 6: S. Edwards, L. Lavagno, E. Lee, A. Sangiovanni-Vincentelli, "Design of Embedded Systems: Formal Models, Validation, and Synthesis," Proc. of the IEEE 85:3 (3/97) 366-390.
• 7: Ove Færgemand , Anders Olsen, Introduction to SDL-92, Computer Networks and ISDN Systems, v.26 n.9, p.1143-1167, May 1994 [doi>10.1016/0169-7552(94)90016-7]
• 8: D. Gajski, F. Vahid, S. Narayan, J. Gong. SpecSyn: An Environment Supporting the Specify-Explore-Refine Paradigm for Hardware/Software System Design. IEEE Transactions on VLSI Systems, Vol. 6, No. 1. March, 1998.
• 9: Ken Hines , Gaetano Borriello, Dynamic communication models in embedded system co-simulation, Proceedings of the 34th annual conference on Design automation, p.395-400, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266178]
• 10: Luciano Lavagno , Ellen Sentovich, ECL: a specification environment for system-level design, Proceedings of the 36th ACM/IEEE conference on Design automation, p.511-516, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309989]
• 11: JoAnn M. Paul , Simon N. Peffers , Donald E. Thomas, A codesign virtual machine for hierarchical, balanced hardware/software system modeling, Proceedings of the 37th conference on Design automation, p.390-395, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337506]
• 12: K. Van Rompaey , I. Bolsens , H. De Man , D. Verkest, CoWare—a design environment for heterogenous hardware/software systems, Proceedings of the conference on European design automation, p.252-257, September 1996, Geneva, Switzerland
• 13: C.L. Seitz. "System Timing." Introduction to VLSI Systems. C. Mead, L. Conway. Reading, MA: Addison-Wesley, 1980.
• 14: David B. Skillicorn , Domenico Talia, Models and languages for parallel computation, ACM Computing Surveys (CSUR), v.30 n.2, p.123-169, June 1998 [doi>10.1145/280277.280278]
• 15: Donald E. Thomas , JoAnn M. Paul , Simon N. Peffers , Sandra J. Weber, Peer-based multithreaded executable co-specification, Proceedings of the seventh international workshop on Hardware/software codesign, p.105-109, March 1999, Rome, Italy [doi>10.1145/301177.301499]
• 16: www.research.digital.com/SRC/personal/mann/chess.html
• 17: http://ucsu.Colorado.EDU/~kerrigat/

INDEX TERMS

Primary Classification:
  D. Software
  D.4 OPERATING SYSTEMS

Additional Classification:
  D. Software
  D.3 PROGRAMMING LANGUAGES

General Terms:
Design, Management

Keywords:
clock domains, computer system modeling, frequency interleaved scheduling, hardware/software codesign