Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session)

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Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session)

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International Workshop on System-Level Interconnect Prediction archive
Proceedings of the 2000 international workshop on System-level interconnect prediction table of contents

San Diego, California, United States

Pages: 147 - 148

Year of Publication: 2000

ISBN:1-58113-249-2

Authors

Jeff A. Davis	Georgia Institute of Technology, School of ECE, Atlanta, GA
Raguraman Venkatesan	Georgia Institute of Technology, School of ECE, Atlanta, GA
Keith Bowman	Georgia Institute of Technology, School of ECE, Atlanta, GA
James D. Meindl	Georgia Institute of Technology, School of ECE, Atlanta, GA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 2, Downloads (12 Months): 16, Citation Count: 5

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cited by index terms collaborative colleagues

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CITED BY 5

	Prashant Saxena , Noel Menezes , Pasquale Cocchini , Desmond A. Kirkpatrick, The scaling challenge: can correct-by-construction design help?, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Tao Lin , Lawrence T. Pileggi, Throughput-driven IC communication fabric synthesis, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.274-279, November 10-14, 2002, San Jose, California
	Vikas Chandra , Anthony Xu , Herman Schmit , Larry Pileggi, An Interconnect Channel Design Methodology for High Performance Integrated Circuits, Proceedings of the conference on Design, automation and test in Europe, p.21138, February 16-20, 2004
	Arkadiy Morgenshtein , Eby G. Friedman , Ran Ginosar , Avinoam Kolodny, Timing optimization in logic with interconnect, Proceedings of the 2008 international workshop on System level interconnect prediction, April 05-08, 2008, Newcastle, United Kingdom
	Michael Moreinis , Arkadiy Morgenshtein , Israel A. Wagner , Avinoam Kolodny, Logic gates as repeaters (LGR) for area-efficient timing optimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.11, p.1276-1281, November 2006