Why interconnect prediction doesn't work

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Why interconnect prediction doesn't work

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International Workshop on System-Level Interconnect Prediction archive
Proceedings of the 2000 international workshop on System-level interconnect prediction table of contents

San Diego, California, United States

Pages: 139 - 144

Year of Publication: 2000

ISBN:1-58113-249-2

Authors

Lou Scheffer	Cadence, 555 River Oaks Parkway, San Jose, CA
Eric Nequist	Cadence, 555 River Oaks Parkway, San Jose, CA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 27, Citation Count: 12

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Landman, B., and Russo, R., "On a Pin Versus Block Relationship for Partitions of Logic Graphs", IEEE transactions on Computing, 20, pp. 1469-1479. (1971)
	2	Trimberger, S., 'A Reprogrammable Gate Array and Applications', Proceedings of the IEEE, Volume: 81 7, July 1993, Page(s): 1030 -1041.
	3	"Tool tightens layout link, ditches wire-load model -- Cadence lays claim to synthesis coup", Electronic Engineering Times, July 12, 1999
	4	"Synthesis takes two giant steps: Synopsys' long-awaited Physical Compiler unites placement with synthesis" , Electronic Engineering Times, Nov. 15, 1999
	5	"Cadence triggers synthesis price war", Electronic Engineering Times, September 13, 1999
	6	"Nano Project would reroute today's synthesis-to-layout flow - Cadence maps design overhaul", Electronic Engineering Times, May 17, 1999

CITED BY 12

	Muzammil Iqbal , Ahmed Sharkawy , Usman Hameed , Phillip Christie, Stochastic wire length sampling for cycle time estimation, Proceedings of the 2002 international workshop on System-level interconnect prediction, April 06-07, 2002, San Diego, California, USA
	Chung-Kuan Cheng , Andrew B. Kahng , Bao Liu , Dirk Stroobandt, Toward better wireload models in the presence of obstacles, Proceedings of the 2001 conference on Asia South Pacific design automation, p.527-532, January 2001, Yokohama, Japan
	Xiaojian Yang , Ryan Kastner , Majid Sarrafzadeh, Congestion estimation during top-down placement, Proceedings of the 2001 international symposium on Physical design, p.164-169, April 01-04, 2001, Sonoma, California, United States
	Amit Singh , Ganapathy Parthasarathy , Malgorzata Marek-Sadowska, Efficient circuit clustering for area and power reduction in FPGAs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.4, p.643-663, October 2002
	Chung-Kuan Cheng , Andrew B. Kahng , Bao Liu , Dirk Stroobandt, Toward better wireload models in the presence of obstacles, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.2, p.177-189, April 2002
	Saurabh N. Adya , Mehmet C. Yildiz , Igor L. Markov , Paul G. Villarrubia , Phiroze N. Parakh , Patrick H. Madden, Benchmarking for large-scale placement and beyond, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Kenneth D. Boese , Andrew B. Kahng , Stafanus Mantik, On the relevance of wire load models, Proceedings of the 2001 international workshop on System-level interconnect prediction, p.91-98, March 31-April 01, 2001, Sonoma, California, United States
	Parivallal Kannan , Shankar Balachandran , Dinesh Bhatia, On metrics for comparing interconnect estimation methods for FPGAs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.4, p.381-385, April 2004
	Qinghua Liu , Malgorzata Marek-Sadowska, Wire length prediction-based technology mapping and fanout optimization, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA
	Andrew B. Kahng , Sherief Reda, A tale of two nets: studies of wirelength progression in physical design, Proceedings of the international workshop on System-level interconnect prediction, March 04-05, 2006, Munich, Germany
	Saurabh N. Adya , Igor L. Markov , Paul G. Villarrubia, On whitespace and stability in physical synthesis, Integration, the VLSI Journal, v.39 n.4, p.340-362, July 2006
	Saurabh N. Adya , Igor L. Markov , Paul G. Villarrubia, On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.311, November 09-13, 2003