Cost based tradeoff analysis of standard cell designs

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Cost based tradeoff analysis of standard cell designs

Full text

Pdf (318 KB)

Source

International Workshop on System-Level Interconnect Prediction archive
Proceedings of the 2000 international workshop on System-level interconnect prediction table of contents

San Diego, California, United States

Pages: 129 - 135

Year of Publication: 2000

ISBN:1-58113-249-2

Authors

Peng Li	Dept. of Electrical & Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Pranab K. Nag	Dept. of Electrical & Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Wojciech Maly	Dept. of Electrical & Computer Engineering, Carnegie Mellon University, Pittsburgh, PA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 7, Downloads (12 Months): 23, Citation Count: 3

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/333032.333043 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Kai-Win Lee and Carl Sechen, "A New Global Router for Row-based Layout," Digest of Technical Papers, ICCAD-88, 180-183 (Nov. 1988).
	2	Patrick Hung , Michael J. Flynn, Stochastic Congestion Model for VLSI Systems, Stanford University, Stanford, CA, 1997
	3	J. T. Mowchenko, "A Lower Bound on Channel Density After Global Routing," IEEE Trans. Computer-aided Design, vol. 8, 574-577 (May 1989).
	4	B.T. Murphy, "Cost size optima of monolithic integrated circuits," Proceedings of the IEEE, vol. 52, 1537-1545 (1964).
	5	R. Seeds, "Yield and cost analysis of bipolar LSI," IEEE Int. Electron Devices Meeting (1967).
	6	R.M. Warner, Jr., "Applying a composite model to the IC yield problem," IEEE J. Solid-State Circuits, vol. SC-9, 86- 95 (June 1974).
	7	C.H. Stapper, "On a composite model to the IC yield problem," IEEE Journal of Solid-State Circuits, vol. SC-10, 537-539 (1975).
	8	C.H. Stapper, A.N. McLaren, and M. Dreckmann, "Yield model for productivity optimization of VLSI memory chips with redundancy and partial good product," IBM Journal of Research and Development, vol. 24, 398-409 (1980).
	9	C.H. Stapper and R.J. Rosner, "A simple method for modeling VLSI yields," Solid State Electronics, vol. 25, 487- 489 (1982).
	10	W. Maly and J. Deszczka, "Yield Estimation Model for VLSI Artwork Evaluation," Electronics Letters, 17th Vol. 19, No. 6, 226-227 (March 1983).
	11	A.V. Ferris-Prabhu, Modeling the critical area in yield forecasts," IEEE Journal of Solid State Circuits, vol. SC-20, no. 4, 874-878 (Aug. 1985).
	12	A. V. Ferris-Prabhu, "Defect size variations and their effect on the critical area of VLSI devices," IEEE Journal Solid-State Circuits, vol. SC-20, 878-880 (Aug. 1985).
	13	W. Maly, "Modeling of lithography-related yield losses for CAD of VLSI circuits," IEEE Transactions on Computer-Aided Design, vol. CAD-4, 161-177 (July 1985).
	14	D.M.H. Walker, "Yield Simulation for Integrated Circuits," Boston: Kluwer Academic Publishers (1987).
	15	Pranab K. Nag and Wojciech Maly, "Yield Estimation of VLSI circuits," Techcon'90, 267-270 (Oct. 1990).
	16	T.L. Michalka, R.C. Varshney, and J.D. Meindl, "A discussion of yield modeling with defect clustering, circuit repair, and circuit redundancy," IEEE Transactions of Semiconductor Manufacturing, vol. 3, no. 3, 116-127 (Aug. 1990) .
	17	18. J. Pineda de Gyvez and C. Di, "IC defect sensitivity for footprint-type spot defects," IEEE Transactions on Computer-Aided Design, vol. 11, no. 5, 638-658 (May 1992).
	18	J. Khare, D.B.I. Feltham and W. Maly, "Accurate Estimation of Defect-Related Yield Loss in Reconfigurable VLSI Circuits," IEEE Journal of Solid-State Circuits, vol. 28, no. 2, 146-156 (Feb. 1993).
	19	P. K. Nag , W. Maly, Hierarchical extraction of critical area for shorts in very large ICs, Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, p.19, November 13-15, 1995
	20	Hans T. Heineken , Wojciech Maly, Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.368-373, November 10-14, 1996, San Jose, California, United States
	21	W. Maly , H. Heineken , J. Khare , P. K. Nag, Design for manufacturability in submicron domain, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.690-697, November 10-14, 1996, San Jose, California, United States
	22	Pranab K. Nag and Wojciech Maly, "Excel Based Cost Model," Technical Report No. CMUCAD-00-10, Carnegie Mellon University (July 1999).
	23	Philip Chong and Robert K. Brayton, "Estimating and Optimizing Routing Utilization in DSM Design," Workshop on System-Level Interconnect Prediction, SLIP' 99, 97-102 (April 1999).
	24	David N. Deutsch, A “Dogleg” channel router, Proceedings of the 13th conference on Design automation, p.425-433, June 28-30, 1976, San Francisco, California, United States [doi>10.1145/800146.804843]
	25	N. Hasan, G. Vijayan and C. K. Wong, "A Neighborhood Improvement Algorithm for Rectilinear Steiner Trees," Int. Symposium on Circuits and Systems, 2869-2872 (1990).
	26	Naveed A. Sherwani, Algorithms for VLSI Physical Design Automation, Kluwer Academic Publishers, Norwell, MA, 1995
	27	Jeremy Zelsnack, "Modeling-Based Optimization of Number of Metal Layers," MS Thesis, Carnegie Mellon University, Report CMUCAD 98-17 (May 1998).
	28	W. R. Heller , W. F. Michail , W. E. Donath, Prediction of wiring space requirements for LSI, Proceedings of the 14th conference on Design automation, p.32-42, January 1977
	29	A. A. El-Gamal, "Two-dimensional Stochastic Model for Interconnections in Master Slice Integrated Circuits," IEEE Trans. On Circuits and Systems, vol. CAS-28, 127-138 (Feb. 1981).
	30	S. Sastry, A. C. Parker, "Stochastic Models for Wireability Analysis of Gate Arrays," IEEE Trans. On Computer-aided Design, vol. CAD-5, 53-65 (Jan.1986).
	31	Kusnadi , Jo Dale Carothers, A method of measuring nets routability for MCM's general area routing problems, Proceedings of the 1999 international symposium on Physical design, p.186-192, April 12-14, 1999, Monterey, California, United States [doi>10.1145/299996.300069]
	32	Jeffery A. Davis, Vivek K. De, and James D. Meindl, "A Stochastic Wire-Length Distribution for Gigascale Integration (GSI)-Part II: Applications to Clock Frequency, Power Dissipation, and Chip Size Estimation", IEEE Trans. On Electron Devices, vol. 45, no. 3 (March 1998).

CITED BY 3

	Phillip Christie , José Pineda de Gyvez, Pre-layout prediction of interconnect manufacturability, Proceedings of the 2001 international workshop on System-level interconnect prediction, p.167-173, March 31-April 01, 2001, Sonoma, California, United States
	Suhrid A. Wadekar , Alice C. Parker, Interconnect-based system-level energy and power prediction to guide architecture exploration, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.4, p.373-380, April 2004
	Robert Aitken, DFM Metrics for Standard Cells, Proceedings of the 7th International Symposium on Quality Electronic Design, p.491-496, March 27-29, 2006