Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures

Full text

Pdf (338 KB)

Source

International Workshop on System-Level Interconnect Prediction archive
Proceedings of the 2000 international workshop on System-level interconnect prediction table of contents

San Diego, California, United States

Pages: 123 - 127

Year of Publication: 2000

ISBN:1-58113-249-2

Authors

James W. Joyner	Georgia Institute of Technology, Atlanta, GA
Payman Zarkesh-Ha	Georgia Institute of Technology, Atlanta, GA
Jeffrey A. Davis	Georgia Institute of Technology, Atlanta, GA
James D. Meindl	Georgia Institute of Technology, Atlanta, GA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 15, Citation Count: 2

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/333032.333042 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	D. A. Antoniadis, A. Wei, A. Lochtefeld, "SOI Devices and Technology," ESSDERC, pp. 81-87, 1999.
	2	A. Rahman, A. Fan, J. Chung, R. Reif, "Wire-Length Distribution of Three-Dimensional Integrated Circuits," IITC, pp. 233-235, 1999.
	3	S. J. Souri, K. C. Saraswat, "Interconnect Performance Modeling for 3D Integrated Circuits with Multiple Si Layers," IITC, pp. 24-26, 1999.
	4	J. W. Joyner, P. Zarkesh-Ha, J. A. Davis, J. D. Meindl, "A Three-Dimensional Stochastic Wire-Length Distribution for Variable Separation of Strata," accepted to IITC, 2000.
	5	J. D. Meindl, "Low Power Microelectronics: Retrospect and Prospect," Proc. IEEE, vol. 83, pp. 619-635, April 1995.
	6	J. D. Meindl, "Interconnection Limits on XXI Century Gigascale Integration (GSI)," Materials Research Society, pp. 3-9, April 1998.
	7	R. Venkatesan, J. A. Davis, J. D. Meindl, "Performance Enhancement Through Optimal N-Tier Multilevel Interconnect Architectures," ASIC/SOC, pp. 19-23, 1999.
	8	J. A. Davis, V. K. De, J. D. Meindl, "A Stochastic Wire-length Distribution for Gigascale Integration (GSI) - Part I: Derivation and Validation," IEEE Trans. Electron Devices, vol. 45, no. 3, pp. 580-589, March 1998.
	9	B. S. Landman and R. L. Russo, "On a Pin Versus Block Relationship For Partitions of Logic Graphs," IEEE Trans. Comput., vol C-20, pp. 1469-1479, Dec. 1971.
	10	H. Van Marck , J. Van Campenhout, Three-dimensional Optoelectronic Architectures for Massively Parallel Processing Systems, Proceedings of the 4th International Conference on Massively Parallel Processing Using Optical Interconnections, p.178, June 22-24, 1997
	11	J. A. Davis, V. K. De, J. D. Meindl, "A Stochastic Wire-length Distribution for Gigascale Integration (GSI) - Part II: Applications to Clock Frequency, Power Dissipation, and Chip Size Estimation," IEEE Trans. Electron Devices, vol. 45, no. 3, pp. 590-597, March 1998.
	12	T. Sakurai, "Closed Form Expressions for Interconnect Delay, Coupling and Crosstalk in VLSI's," IEEE Trans. Electron Devices, vol. 40, pp. 118-124, Jan. 1993.
	13	Semiconductor Industry Association, "ITRS", 1999.
	14	J. H. Chern, et al., "Multilevel Metal Capacitance Models for CAD Design Synthesis Systems," IEEE Electron Device Letters, vol. 13, no. 1, Jan. 1992.
	15	Interconnect Focus Center, "Interconnect Focus Center Annual Review - Task V," http://www.ifc.gatech.edu/reports/pdf/1999q4/task5.pdf, Dec. 1999.
	16	J. A. Cunningham, "The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing," IEEE Trans. Semiconductor Manufacturing, vol. 3, no. 2, pp. 60-71, May 1990.

CITED BY 2

	Phillip Christie , José Pineda de Gyvez, Pre-layout prediction of interconnect manufacturability, Proceedings of the 2001 international workshop on System-level interconnect prediction, p.167-173, March 31-April 01, 2001, Sonoma, California, United States
	Phillip Christie , José Pineda de Gyvez, Prelayout interconnect yield prediction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.55-59, February 2003