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Wiring layer assignments with consistent stage delays
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Source International Workshop on System-Level Interconnect Prediction archive
Proceedings of the 2000 international workshop on System-level interconnect prediction table of contents
San Diego, California, United States
Pages: 115 - 122  
Year of Publication: 2000
ISBN:1-58113-249-2
Authors
Andrew B. Kahng  University of California at Los Angeles, CS Dept., 3731 Boelter Hall, Los Angeles, CA
Dirk Stroobandt  Ghent University, ELIS Dept., Sint-Pietersnieuwstraat 41, B-9000 Gent, Belgium
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 1,   Downloads (12 Months): 15,   Citation Count: 5
Additional Information:

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
J. Lillis, C.-K. Cheng, and T.-T.Y. Lin. \Optimal wire sizing and bu~er insertion for low power and a generalized delay model." In IEEE J. Solid-State Circuits, 31 (3): pp. 437{447, 1995.
 
2
Chris C. N. Chu , D. F. Wong, A new approach to simultaneous buffer insertion and wire sizing, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.614-621, November 09-13, 1997, San Jose, California, United States
3
Charles J. Alpert , Anirudh Devgan , Stephen T. Quay, Buffer insertion for noise and delay optimization, Proceedings of the 35th annual conference on Design automation, p.362-367, June 15-19, 1998, San Francisco, California, United States  [doi>10.1145/277044.277145]
4
Andrew E. Caldwell , Yu Cao , Andrew B. Kahng , Farinaz Koushanfar , Hua Lu , Igor L. Markov , Michael Oliver , Dirk Stroobandt , Dennis Sylvester, GTX: the MARCO GSRC technology extrapolation system, Proceedings of the 37th conference on Design automation, p.693-698, June 05-09, 2000, Los Angeles, California, United States  [doi>10.1145/337292.337617]
5
Ralph H. J. M. Otten , Robert K. Brayton, Planning for performance, Proceedings of the 35th annual conference on Design automation, p.122-127, June 15-19, 1998, San Francisco, California, United States  [doi>10.1145/277044.277071]
 
6
P. Chong and R. K. Brayton. \Estimating and optimizing routing utilization in DSM design." In Workshop notes 1st Intl. Workshop on System-Level Interconnect Prediction, pp. 97{102, 1999.
 
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8
Dennis Sylvester , Kurt Keutzer, Getting to the bottom of deep submicron, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.203-211, November 08-12, 1998, San Jose, California, United States  [doi>10.1145/288548.288614]
 
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D. Sylvester and K. Keutzer. \System-level performance modeling with BACPAC { Berkeley advanced chip performance calculator." In Workshop notes 1st Intl. Workshop on System-Level Interconnect Prediction, pp. 109{114, 1999.
 
10
Charles J. Alpert , Anirudh Devgan , Stephen T. Quay, Is wire tapering worthwhile?, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.430-436, November 07-11, 1999, San Jose, California, United States
 
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G. A. Sai-Halasz. \Performance trends in high-performance processors." In Proc. IEEE, pp. 20{36, 1995.
 
12
Q. Chen, J.A. Davis, P. Zarkesh-Ha, and J.D. Meindl. \Via impact and via-limited chip size," 1999. Georgia Inst. of Techn. Private communication.
13
Andrew B. Kahng , Stefanus Mantik , Dirk Stroobandt, Requirements for models of achievable routing, Proceedings of the 2000 international symposium on Physical design, p.4-11, May 2000, San Diego, California, United States  [doi>10.1145/332357.332364]
 
14
W. E. Donath. \Placement and average interconnection lengths of computer logic." IEEE Trans. Circuits & Syst., CAS{26: pp. 272{277, 1979.
 
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W. E. Donath. \Wire length distribution for placements of computer logic." IBM J. of Research and Development, 25: pp. 152{155, 1981.
 
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J. A. Davis, V. K. De, and J. D. Meindl. \A stochastic wire-length distribution for gigascale integration (GSI) { PART I: Derivation and validation." IEEE Trans. on Electron Devices, 45 (3): pp. 580{589, 1998.
 
17
D. Stroobandt and J. Van Campenhout. \Accurate interconnection length estimations for predictions early in the design cycle." VLSI Design, Special Issue on Physical Design in Deep Submicron, 10, 1999.
 
18
B. S. Landman and R. L. Russo. \On a pin versus block relationship for partitions of logic graphs." IEEE Trans. on Comput., C{20: pp. 1469{1479, 1971.
 
19
Philip Christie , Dirk Stroobandt, The interpretation and application of Rent's rule, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.8 n.6, p.639-648, Dec. 2000  [doi>10.1109/92.902258]
 
20
A. B. Kahng and D. Stroobandt. \Wiring layer assignments with consistent stage delay." Technical Report CSD-200005, UCLA CS Dept., March 2000.

CITED BY  5
Phillip Christie , José Pineda de Gyvez, Pre-layout prediction of interconnect manufacturability, Proceedings of the 2001 international workshop on System-level interconnect prediction, p.167-173, March 31-April 01, 2001, Sonoma, California, United States
Phillip Christie , José Pineda de Gyvez, Prelayout interconnect yield prediction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.55-59, February 2003
Raguraman Venkatesan , Jeffrey A. Davis , Keith A. Bowman , James D. Meindl, Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI), IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.6, p.899-912, 12/1/2001
Dirk Stroobandt, A priori wire length distribution models with multiterminal nets, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.35-43, February 2003
Parthasarathi Dasgupta , Andrew B. Kahng , Swamy Muddu, A Novel Metric for Interconnect Architecture Performance, Proceedings of the conference on Design, Automation and Test in Europe, p.10448, March 03-07, 2003

INDEX TERMS

Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Placement and routing

  I. Computing Methodologies
  I.6 SIMULATION AND MODELING
      I.6.5 Model Development
          Subjects: Modeling methodologies

  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING
      Subjects: Computer-aided design (CAD)


General Terms:
Design, Measurement, Performance, Theory


Keywords:
delay, layer assignment, routing, via impact, wire length

Collaborative Colleagues:
Andrew B. Kahng: colleagues
Dirk Stroobandt: colleagues

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