Pre-layout estimation of individual wire lengths

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Pre-layout estimation of individual wire lengths

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International Workshop on System-Level Interconnect Prediction archive
Proceedings of the 2000 international workshop on System-level interconnect prediction table of contents

San Diego, California, United States

Pages: 93 - 98

Year of Publication: 2000

ISBN:1-58113-249-2

Authors

Srinivas Bodapati	ECE Dept. and Coordinated Science Lab., University of Illinois at Urbana-Champaign, Urbana, Illinois
Farid N. Najm	ECE Department, University of Toronto, Toronto, Ontario M5S-3G4, Canada

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 15, Citation Count: 14

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Hema Kapadia , Mark Horowitz, Using partitioning to help convergence in the standard-cell design automation methodology, Proceedings of the 36th ACM/IEEE conference on Design automation, p.592-597, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.310005]
	2	Paul McLellan,"The radical changes wrought by deep submicr n IC technology,"EDA Today Summary Re-0 port ,vol.1,no.6,June 1995.
	3	H.T.Heineken and W.Maly,"Standard cell interconnect length prediction from structural circuit attributes,"Proc. Custom Integrated Circuits Conference ,pp.167 -170,May 1996.
	4	T.Hamada,C.-K.Cheng and P.M.Chau "A wire length estimati n technique utilizing neighb rh d density equati ns,"IEEE Transactions on Computer-Aided Desig ,vol.15 pp.912 -922,August 1996.
	5	M.Pedram and B.T.Preas,"Interconnecti n length estimati n for ptimized standard cell lay uts,"Inter-400.0 national Conference on Computer Design ,pp.390 -393, Oct ber 1989.
	6	A.E.Caldwell,A.B.Kahng,S.Mantik,I.L.Mark v and A.Zelik vsky,"On wirelength estimations for rowbased placement,"IEEE Transactions on Computer-Estimated Aided Desig ,pp.1265 -1278,Sep 1999.

CITED BY 14

	Qinghua Liu , Bo Hu , Malgorzata Marek-Sadowska, Wire length prediction in constraint driven placement, Proceedings of the 2003 international workshop on System-level interconnect prediction, April 05-06, 2003, Monterey, CA, USA
	Padmini Gopalakrishnan , Altan Odabasioglu , Lawrence Pileggi , Salil Raje, Overcoming wireload model uncertainty during physical design, Proceedings of the 2001 international symposium on Physical design, p.182-189, April 01-04, 2001, Sonoma, California, United States
	Bo Hu , Malgorzata Marek-Sadowska, Wire length prediction based clustering and its application in placement, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Pranav Anbalagan , Jeffrey A. Davis, A priori prediction of tightly clustered connections based on heuristic classification trees, Proceedings of the international workshop on System-level interconnect prediction, March 04-05, 2006, Munich, Germany
	Kenneth D. Boese , Andrew B. Kahng , Stafanus Mantik, On the relevance of wire load models, Proceedings of the 2001 international workshop on System-level interconnect prediction, p.91-98, March 31-April 01, 2001, Sonoma, California, United States
	Shankar Balachandran , Dinesh Bhatia, A-priori wirelength and interconnect estimation based on circuit characteristics, Proceedings of the 2003 international workshop on System-level interconnect prediction, April 05-06, 2003, Monterey, CA, USA
	Qinghua Liu , Malgorzata Marek-Sadowska, Pre-layout wire length and congestion estimation, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Qinghua Liu , Malgorzata Marek-Sadowska, Wire length prediction-based technology mapping and fanout optimization, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA
	Jason H. Anderson , Farid N. Najm, Power estimation techniques for FPGAs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.10, p.1015-1027, October 2004
	Qinghua Liu , Bo Hu , Malgorzata Marek-Sadowska, Individual wire-length prediction with application to timing-driven placement, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.10, p.1004-1014, October 2004
	Valavan Manohararajah , Gordon R. Chiu , Deshanand P. Singh , Stephen D. Brown, Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow, Proceedings of the international workshop on System-level interconnect prediction, March 04-05, 2006, Munich, Germany
	Jason H. Anderson , Farid N. Najm, Interconnect capacitance estimation for FPGAs, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.713-718, January 27-30, 2004, Yokohama, Japan
	A. B. Kahng , S. Reda, Intrinsic shortest path length: a new, accurate a priori wirelength estimator, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.173-180, November 06-10, 2005, San Jose, CA
	Valavan Manohararajah , Gordon R. Chiu , Deshanand P. Singh , Stephen D. Brown, Predicting interconnect delay for physical synthesis in a FPGA CAD flow, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.8, p.895-903, August 2007