Performance analysis and technology of 3-D ICs

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Performance analysis and technology of 3-D ICs

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International Workshop on System-Level Interconnect Prediction archive
Proceedings of the 2000 international workshop on System-level interconnect prediction table of contents

San Diego, California, United States

Pages: 85 - 90

Year of Publication: 2000

ISBN:1-58113-249-2

Authors

Krishna C. Saraswat	Department of Electrical Engineering, Stanford University, Stanford, CA
Shukri J. Souri	Department of Electrical Engineering, Stanford University, Stanford, CA
Kaustav Banerjee	Department of Electrical Engineering, Stanford University, Stanford, CA
Pawan Kapur	Department of Electrical Engineering, Stanford University, Stanford, CA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 22, Citation Count: 3

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 3

	Xiaojian Yang , Elaheh Bozorgzadeh , Majid Sarrafzadeh, Wirelength estimation based on rent exponents of partitioning and placement, Proceedings of the 2001 international workshop on System-level interconnect prediction, p.25-31, March 31-April 01, 2001, Sonoma, California, United States
	Viet H. Nguyen , Phillip Christie, The impact of interstratal interconnect density on the performance of three-dimensional integrated circuits, Proceedings of the 2005 international workshop on System level interconnect prediction, April 02-03, 2005, San Francisco, California, USA
	Joni Dambre , Dirk Stroobandt , Jan Van Campenhout, Toward the accurate prediction of placement wire length distributions in VLSI circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.4, p.339-348, April 2004