Theoretical limits for signal reflections due to inductance for on-chip interconnections

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Theoretical limits for signal reflections due to inductance for on-chip interconnections

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International Workshop on System-Level Interconnect Prediction archive
Proceedings of the 2000 international workshop on System-level interconnect prediction table of contents

San Diego, California, United States

Pages: 55 - 60

Year of Publication: 2000

ISBN:1-58113-249-2

Authors

D. Deschacht	Laboratoire d'Informatique, de Robotique et de Microélectronique, U.M.R. C.N.R.S. 5506, 161, rue ADA, 34392 Montpellier Cedex 5, France
G. Servel	Laboratoire d'Informatique, de Robotique et de Microélectronique, U.M.R. C.N.R.S. 5506, 161, rue ADA, 34392 Montpellier Cedex 5, France
F. Huret	Institut d'Electronique et de Microélectronique du Nord, U.M.R. C.N.R.S. 9929, Département Hyperfréquences et Semiconducteurs, Cité Scientifique, Avenue Poincaré, B.P. 69, 59652, Villeneuve d'Ascq, France
E. Paleczny	Institut d'Electronique et de Microélectronique du Nord, U.M.R. C.N.R.S. 9929, Département Hyperfréquences et Semiconducteurs, Cité Scientifique, Avenue Poincaré, B.P. 69, 59652, Villeneuve d'Ascq, France
P. Kennis	Institut d'Electronique et de Microélectronique du Nord, U.M.R. C.N.R.S. 9929, Département Hyperfréquences et Semiconducteurs, Cité Scientifique, Avenue Poincaré, B.P. 69, 59652, Villeneuve d'Ascq, France

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SIGDA: ACM Special Interest Group on Design Automation

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ACM New York, NY, USA

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Downloads (6 Weeks): 2, Downloads (12 Months): 9, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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