Routability-driven repeater block planning for interconnect-centric floorplanning

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Routability-driven repeater block planning for interconnect-centric floorplanning

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International Symposium on Physical Design archive
Proceedings of the 2000 international symposium on Physical design table of contents

San Diego, California, United States

Pages: 186 - 191

Year of Publication: 2000

ISBN:1-58113-191-7

Authors

Probir Sarkar	School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Vivek Sundararaman	School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Cheng-Kok Koh	School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 11, Citation Count: 21

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Charles Alpert , Anirudh Devgan, Wire segmenting for improved buffer insertion, Proceedings of the 34th annual conference on Design automation, p.588-593, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266291]
	2	H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI, Addison-Wesley, 1990.
	3	Hung-Ming Chen , Hai Zhou , F. Y. YOung , D. F. Wong , Hannah H. Yang , Naveed Sherwani, Integrated floorplanning and interconnect planning, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.354-357, November 07-11, 1999, San Jose, California, United States
	4	Chris C. N. Chu , D. F. Wong, Closed form solution to simultaneous buffer insertion/sizing and wire sizing, Proceedings of the 1997 international symposium on Physical design, p.192-197, April 14-16, 1997, Napa Valley, California, United States [doi>10.1145/267665.267712]
	5	J. Cong, "Challenges and Opportunities for Design Innovation in Nanometer Technologies", SRC Working Papers, 1997.
	6	Jason Cong , Zhigang Pan , Lei He , Cheng-Kok Koh , Kei-Yong Khoo, Interconnect design for deep submicron ICs, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.478-485, November 09-13, 1997, San Jose, California, United States
	7	Jason Cong , Lei He , Cheng-Kok Koh , Patrick H. Madden, Performance optimization of VLSI interconnect layout, Integration, the VLSI Journal, v.21 n.1-2, p.1-94, Nov. 1996 [doi>10.1016/S0167-9260(96)00008-9]
	8	Jason Cong , Tianming Kong , David Zhigang Pan, Buffer block planning for interconnect-driven floorplanning, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.358-363, November 07-11, 1999, San Jose, California, United States
	9	J. Cong, T. Kong, and D.Z. Pan, Personal Communication
	10	Jason Cong, T. Kong, D. Xu, E Liang, J. S. Liu and W. H. Wong, "Relaxed Simulated Tempering for VLSI Floorplan Design", Proc. Asia and South Pacific Design Automation Conference, pp. 13-16, 1999.
	11	Jason Cong , Patrick H. Madden, Performance driven multi-layer general area routing for PCB/MCM designs, Proceedings of the 35th annual conference on Design automation, p.356-361, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277144]
	12	J. Cong and D.Z. Pan, "Interconnect Delay Estimation Models for Synthesis and Design Planning", Proc. Asia South Pacific Design Automation Conference, pp. 97-100, 1999
	13	W.C. Elmore, "The Transient Response of Damped Linear Networks with particular regard to Wide-Band Amplifiers", Journal of Applied Physics, 19(1), pp. 55-63, 1948.
	14	Maggie Kang , Wayne W.-M. Dai , Tom Dillinger , David LaPotin, Delay bounded buffered tree construction for timing driven floorplanning, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.707-712, November 09-13, 1997, San Jose, California, United States
	15	John Lillis , Chung-Kuan Cheng , Ting-Ting Y. Lin, Optimal wire sizing and buffer insertion for low power and a generalized delay model, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.138-143, November 05-09, 1995, San Jose, California, United States
	16	Ralph Linsker, An iterative-improvement penalty-function-driven wire routing system, IBM Journal of Research and Development, v.28 n.5, p.613-624, September 1984
	17	http://www.cbl.ncsu.edu/cbl_ docs/lys92.html
	18	R. Otten, "Graphs in Floor-plan Design," International Journal of Circuit Theory and Applications, vol. 16, pp. 391-410, Oct. 1988.
	19	Ralph H. J. M. Otten, Global wires: harmful?, Proceedings of the 1998 international symposium on Physical design, p.104-109, April 06-08, 1998, Monterey, California, United States [doi>10.1145/274535.274550]
	20	Patrick H. Madden, Partitioning by iterative deletion, Proceedings of the 1999 international symposium on Physical design, p.83-89, April 12-14, 1999, Monterey, California, United States [doi>10.1145/299996.300030]
	21	Hiroshi Murata , Kunihiro Fujiyoshi , Shigetoshi Nakatake , Yoji Kajitani, Rectangle-packing-based module placement, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.472-479, November 05-09, 1995, San Jose, California, United States
	22	Takumi Okamoto , Jason Cong, Buffered Steiner tree construction with wire sizing for interconnect layout optimization, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.44-49, November 10-14, 1996, San Jose, California, United States
	23	P. Sarkar, V. Sundararaman, C.-K. Koh, "Routability-Driven Repeater Block Planning for Interconnect-Centric Floorplanning", manuscript available at http://dynamo.ecn.purdue.edu/~chengkoh/work.html.
	24	Semiconductor Industry Association, National Semiconductor Roadmap for Semiconductors, 1997.
	25	H. Shin and A. Sangiovanni-Vincentelli, "A detailed router based on incremental routing modifications: MIGHTY", IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, CAD-6(6), pp. 942-955, 1987.
	26	E. Shragowitz , S. Keel, A global router based on a multicommodity flow model, Integration, the VLSI Journal, v.5 n.1, p.3-16, March 1987 [doi>10.1016/S0167-9260(87)80003-2]
	27	L.P.EP. van Ginneken, "Buffer placement in distributed RC-tree Networks for Minimal Elmore Delay", Proc. IEEE Int. Symposium on Circuits and Systems, pp. 865-868, 1990.
	28	D. Wong and C.L. Liu, "Floorplan Design of VLSI circuits", in A1- gorithmica, pp. 263-291, 1989.

CITED BY 21

	Chiu Wing Sham , Evangeline F. Y. Young, Routability driven floorplanner with buffer block planning, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	Yuchun Ma , Xianlong Hong , Sheqin Dong , Song Chen , Yici Cai , C. K. Cheng , Jun Gu, An integrated floorplanning with an efficient buffer planning algorithm, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	P. Sarkar , C. Koh, Repeater block planning under simultaneous delay and transition time constraints, Proceedings of the conference on Design, automation and test in Europe, p.540-545, March 2001, Munich, Germany
	Charles J. Alpert , Jiang Hu , Sachin S. Sapatnekar , Paul Villarrubia, A practical methodology for early buffer and wire resource allocation, Proceedings of the 38th conference on Design automation, p.189-194, June 2001, Las Vegas, Nevada, United States
	Yuchun Ma , Xianlong Hong , Sheqin Dong , Song Chen , Yici Cai , C. K. Cheng , Jun Gu, Dynamic global buffer planning optimization based on detail block locating and congestion analysis, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Yi-Hui Cheng , Yao-Wen Chang, Integrating buffer planning with floorplanning for simultaneous multi-objective optimization, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.624-627, January 27-30, 2004, Yokohama, Japan
	Zion Cien Shen , Chris C. N. Chu, Accurate and efficient flow based congestion estimation in floorplanning, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.671-676, January 27-30, 2004, Yokohama, Japan
	Yuchun Ma , Xianlong Hong , Sheqin Dong , Song Chen , Yici Cai , Chung-Kuan Cheng , Jun Gu, Buffer allocation algorithm with consideration of routing congestion, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.621-623, January 27-30, 2004, Yokohama, Japan
	Hsun-Cheng Lee , Yao-Wen Chang , Jer-Ming Hsu , Hannah H. Yang, Multilevel floorplanning/placement for large-scale modules using B*-trees, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Hua Xiang , D. F. Wong , Xiaoping Tang, An algorithm for integrated pin assignment and buffer planning, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Song Chen , Xianlong Hong , Sheqin Dong , Yuchun Ma , Yici Cai , Chung-Kuan Cheng , Jun Gu, A buffer planning algorithm with congestion optimization, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.615-620, January 27-30, 2004, Yokohama, Japan
	Jason Cong , Tianming Kong , Zhigang (David) Pan, Buffer block planning for interconnect planning and prediction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.6, p.929-937, 12/1/2001
	Hua Xiang , Xiaoping Tang , Martin D. F. Wong, An algorithm for integrated pin assignment and buffer planning, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.3, p.561-572, July 2005
	Song Chen , Xianlong Hong , Sheqin Dong , Yuchun Mal , Yici Cai , Chung-Kuan Cheng , Jun Gu, A buffer planning algorithm based on dead space redistribution, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Iris Hui-Ru Jiang , Yao-Wen Chang , Jing-Yang Jou , Kai-Yuan Chao, Simultaneous floorplanning and buffer block planning, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Xiaoping Tang , D. F. Wong, Planning buffer locations by network flows, Proceedings of the 2000 international symposium on Physical design, p.180-185, May 2000, San Diego, California, United States
	Ou He , Sheqin Dong , Jinian Bian , Yuchun Ma , Xianlong Hong, An effective buffer planning algorithm for IP based fixed-outline SOC placement, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	Ali Jahanian , Morteza Saheb Zamani, Improved timing closure by early buffer planning in floor-placement design flow, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	I-Min Liu , Hung-Ming Chen , Tan-Li Chou , Adnan Aziz , D. F. Wong, Integrated power supply planning and floorplanning, Proceedings of the 2001 conference on Asia South Pacific design automation, p.589-594, January 2001, Yokohama, Japan
	Ruibing Lu , Cheng-Kok Koh, Interconnect Planning with Local Area Constrained Retiming, Proceedings of the conference on Design, Automation and Test in Europe, p.10442, March 03-07, 2003
	Steve T. W. Lai , Evangeline F. Y. Young , Chris C. N. Chu, Handling routability in floorplan design with twin binary trees, Integration, the VLSI Journal, v.42 n.4, p.449-456, September, 2009

Collaborative Colleagues:

Probir Sarkar: colleagues

Vivek Sundararaman: colleagues

Cheng-Kok Koh: colleagues

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