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Floorplan area minimization using Lagrangian relaxation
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Source International Symposium on Physical Design archive
Proceedings of the 2000 international symposium on Physical design table of contents
San Diego, California, United States
Pages: 174 - 179  
Year of Publication: 2000
ISBN:1-58113-191-7
Authors
F. Y. Young  Department of Computer Science and Engineering, The Chinese University of Hong Kong, New Territories, Hong Kong
Chris C. N. Chu  Department of Electrical and Computer Engineering, Iowa State University, Ames, IA
W. S. Luk  Synopsys, Inc., 700 East Middlefield Road, Mountain View, CA
Y. C. Wong  Synopsys, Inc., 700 East Middlefield Road, Mountain View, CA
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 8,   Downloads (12 Months): 26,   Citation Count: 2
Additional Information:

references   cited by   collaborative colleagues  

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
M. Kang and W. W.M. Dai. General Floorplanning with L-shaped, T-shaped and Soft Blocks Based on Bounded Slicing Grid Structure. IEEE Asia and South Pacific Design Automation Conference, pages 265-270, 1997.
 
2
T.-S. Moh, T.-S. Chang, and S. L. Hakimi. Globally Optimal Floorplanning for a Layout Problem. IEEE Transaction on Circuit and Systems - I: Fundamental Theory and Applications, 43(9):713-720, 1996.
 
3
M.S. Bazaraa and H.D. Sherali and C.M. Sherry. Nonlinear Programming: Theory and Algorithms. John Wiley & Sons, Inc., second edition, 1997.
4
Hiroshi Murata , Ernest S. Kuh, Sequence-pair based placement method for hard/soft/pre-placed modules, Proceedings of the 1998 international symposium on Physical design, p.167-172, April 06-08, 1998, Monterey, California, United States  [doi>10.1145/274535.274560]
 
5
Shigetoshi Nakatake , Kunihiro Fujiyoshi , Hiroshi Murata , Yoji Kajitani, Module placement on BSG-structure and IC layout applications, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.484-491, November 10-14, 1996, San Jose, California, United States
 
6
Peichen Pan , C. L. Liu, Area minimization for general floorplans, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.606-609, November 1992, Santa Clara, California, United States
 
7
Larry Stockmeyer, Optimal orientations of cells in slicing floorplan designs, Information and Control, v.57 n.2-3, p.91-101, May/June 1983  [doi>10.1016/S0019-9958(83)80038-2]
8
Ting-chi Wang , D. F. Wong, An optimal algorithm for floorplan area optimization, Proceedings of the 27th ACM/IEEE conference on Design automation, p.180-186, June 24-27, 1990, Orlando, Florida, United States  [doi>10.1145/123186.123253]
 
9
Ting-Chi Wang and D.F. Wong. Optimal Floorplan Area Optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2(8):992-1001, 1992.
 
10
D. F. Wong , C. L. Liu, A new algorithm for floorplan design, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.101-107, July 1986, Las Vegas, Nevada, United States

CITED BY  2
Hsun-Cheng Lee , Yao-Wen Chang , Jer-Ming Hsu , Hannah H. Yang, Multilevel floorplanning/placement for large-scale modules using B*-trees, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
Iris Hui-Ru Jiang , Yao-Wen Chang , Jing-Yang Jou , Kai-Yuan Chao, Simultaneous floorplanning and buffer block planning, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
Collaborative Colleagues:
F. Y. Young: colleagues
Chris C. N. Chu: colleagues
W. S. Luk: colleagues
Y. C. Wong: colleagues

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