An enhanced perturbing algorithm for floorplan design using the O-tree representation

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An enhanced perturbing algorithm for floorplan design using the O-tree representation

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International Symposium on Physical Design archive
Proceedings of the 2000 international symposium on Physical design table of contents

San Diego, California, United States

Pages: 168 - 173

Year of Publication: 2000

ISBN:1-58113-191-7

Authors

Yingxin Pang	Dept. of CSE, Univ. of California, San Diego, La Jolla, CA
Chung-Kuan Cheng	Dept. of CSE, Univ. of California, San Diego, La Jolla, CA
Takeshi Yoshimura	NEC Corp., 4-1-1 Miyazaki, Miyanae-Ku, Kawasaki 216, Japan

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 18, Citation Count: 14

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Thomas T. Cormen , Charles E. Leiserson , Ronald L. Rivest, Introduction to algorithms, MIT Press, Cambridge, MA, 1990
	2	Pei-Ning Guo , Chung-Kuan Cheng , Takeshi Yoshimura, An O-tree representation of non-slicing floorplan and its applications, Proceedings of the 36th ACM/IEEE conference on Design automation, p.268-273, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309928]
	3	H. Murata, K. Fujiyoshi, S. Nakatake, Y. Kajitani, "VLSI module placement based on rectangle-packing by the sequence-pair," IEEE Trans. on Comp. Aided Design of lC's and Systems, Vol. 15, No. 12, pp. 1518-1524, Dec. 1996.
	4	S. Nakatake, K. Fujiyoshi, H. Murata, Y. Kajitani, "Module packing based on the BSG-structure and IC layout applications," IEEE Trans. on Comp. Aided Design of lC's and Systems, Vol.17, No.6, pp. 519-530, June 1998.
	5	R. Otten, "Complexity and diversity in IC layout design" Proc. IEEE Intn 'l Symp. Circuits and Computers, 1980.
	6	D. F. Wong , C. L. Liu, A new algorithm for floorplan design, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.101-107, July 1986, Las Vegas, Nevada, United States

CITED BY 14

	Yingxin Pang , Chung-Kuan Cheng , Koen Lampaert , Weize Xie, Rectilinear block packing using O-tree representation, Proceedings of the 2001 international symposium on Physical design, p.156-161, April 01-04, 2001, Sonoma, California, United States
	Xiaoping Tang , D. F. Wong, FAST-SP: a fast algorithm for block placement based on sequence pair, Proceedings of the 2001 conference on Asia South Pacific design automation, p.521-526, January 2001, Yokohama, Japan
	Jai-Ming Lin , Yao-Wen Chang, TCG: a transitive closure graph-based representation for non-slicing floorplans, Proceedings of the 38th conference on Design automation, p.764-769, June 2001, Las Vegas, Nevada, United States
	Sheqin Dong , Shuo Zhou , Xianlong Hong , Chungkuan Cheng , Jun Gu , Yici Cai, An optimum placement search algorithm based on extended corner block list, Journal of Computer Science and Technology, v.17 n.6, p.699-707, November 2002
	Shuo Zhou , Sheqin Dong , Chung-Kuan Cheng , Jun Gu, ECBL: an extended corner block list with solution space including optimum placement, Proceedings of the 2001 international symposium on Physical design, p.150-155, April 01-04, 2001, Sonoma, California, United States
	M. Lai , D. Wong, Slicing tree is a complete floorplan representation, Proceedings of the conference on Design, automation and test in Europe, p.228-232, March 2001, Munich, Germany
	Jai-Ming Lin , Yao-Wen Chang , Shih-Ping Lin, Corner sequence: a P-admissible floorplan representation with a worst case linear-time packing scheme, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.4, p.679-686, August 2003
	T. Serdar , C. Sechen, Automatic datapath tile placement and routing, Proceedings of the conference on Design, automation and test in Europe, p.552-559, March 2001, Munich, Germany
	Jai-Ming Lin , Yao-Wen Chang, TCG-S: orthogonal coupling of P*-admissible representations for general floorplans, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Yan Feng , Dinesh P. Mehta , Hannah Yang, Constrained "Modern" Floorplanning, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	S. N. Adya , I. L. Markov, Combinatorial techniques for mixed-size placement, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.1, p.58-90, January 2005
	Hayward H. Chan , Saurabh N. Adya , Igor L. Markov, Are floorplan representations important in digital design?, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA
	Lei Cheng , Liang Deng , Martin D. F. Wong, Floorplanning for 3-D VLSI design, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Wenqi Huang , Duanbing Chen , Ruchu Xu, A new heuristic algorithm for rectangle packing, Computers and Operations Research, v.34 n.11, p.3270-3280, November, 2007

Collaborative Colleagues:

Yingxin Pang: colleagues

Chung-Kuan Cheng: colleagues

Takeshi Yoshimura: colleagues

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