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Multi-center congestion estimation and minimization during placement
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Source International Symposium on Physical Design archive
Proceedings of the 2000 international symposium on Physical design table of contents
San Diego, California, United States
Pages: 147 - 152  
Year of Publication: 2000
ISBN:1-58113-191-7
Authors
Maogang Wang  Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL
Xiaojian Yang  Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL
Kenneth Eguro  Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL
Majid Sarrafzadeh  Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 2,   Downloads (12 Months): 13,   Citation Count: 13
Additional Information:

references   cited by   collaborative colleagues  

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
P. Christie. "A Fractal Analysis of Interconnection Complexity". IEEE Transactions on Computer Aided Design, 81(10):1492-1499, 1993.
 
2
P. Larsson and C. Svensson. "Noise in Digital Dynamic CMOS Circuits". IEEE Journal of Solid-State Circuits, pages 655-662, June 1994.
 
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4
M. Marek-Sadowska. "Issues in Timing Driven Layout". pages 1-24, 1993. M. Sarrafzadeh and D. T. Lee, editors.
 
5
S. Mayrhofer and U. Lauther. "Congestion-Driven Placement Using a New Multi-Partitioning Heurist ic". In International Conference on Computer-Aided Design, pages 332-335. IEEE/ACM, November 1990.
 
6
R. Nair, C. L. Berman, P. S. Hauge, and E. J. Yoffa. "Generation of Performance Constraints for Layout". IEEE Transactions on Computer Aided Design, CAD-8(8):860-874, August 1989.
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10
S. Sastry and A. C. Parker. "Stochastic Models for Wireability Analysis of Gate Arrays". IEEE Transactions on Computer Aided Design, Cad-1(1):52-65, 1986.
 
11
K. L. Shepard, V. Narayanan, and R. Rose. "Harmony: Static Noise Analysis of Deep Submicron Digital Integrated Circuits". IEEE Transactions on Computer Aided Design, 18(8):1132-1150, 1999.
 
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CITED BY  13
Collaborative Colleagues:
Maogang Wang: colleagues
Xiaojian Yang: colleagues
Kenneth Eguro: colleagues
Majid Sarrafzadeh: colleagues