| A hybrid dynamic/quadratic programming algorithm for interconnect tree optimization |
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International Symposium on Physical Design
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Proceedings of the 2000 international symposium on Physical design
table of contents
San Diego, California, United States
Pages: 134 - 139
Year of Publication: 2000
ISBN:1-58113-191-7
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Authors
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Yu-Yen Mo
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Department of Electrical and Computer Engineering, Iowa State University, Ames, IA
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Chris Chu
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Department of Electrical and Computer Engineering, Iowa State University, Ames, IA
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Downloads (6 Weeks): 0, Downloads (12 Months): 5, Citation Count: 5
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 REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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C.C.N. Chu and D. F. Wong. "A Quadratic Programming Approach to Simultaneous Buffer Insertion/Sizing and Wire Sizing." IEEE Transactions on Computer-Aided Design, vol. 18, no. 6, pages 787-798, June 1999.
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J. Lillis, C.-K. Cheng, and T.-T. Lin. "Optimal and Efficient Buffer Insertion and Wire Sizing." Proc. Of Custom Integrated Circuit Conf., pages 259-262, 1995.
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Semiconductor Industry Association. The International Technology Roadmap for Semiconductors. 1999.
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L.P.P.P. van Ginneken. "Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay." Proc. Intl. Syrup. on Circuits and Systems, pages 865-868, 1990.
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J. Lillis, C.-K. Cheng, and T.-T. Lin. "Optimal Wire Sizing and Buffer Insertion for Low Power and a Generalized Delay Model." IEEE J. Solid-State Circuits, 31(3):437-447, March, 1996.
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M. Lai and D. F. Wong, "A Memory-Efficient Implementation of Dynamic Programming for Interconnect Optimization." manuscript.
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W.C. Elmore, "The Transient Response of Damped Linear Network with Particular Regard to Wideband Amplifiers." J. Applied Physics, 19:55-63, 1948.
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D.G. Luenberger. Linear and Nonlinear Programming. Addison Wesley, second edition. 1984.
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J. Cong and Z. Pan, "Interconnect Delay Estimation Models for Synthesis and Design Planning." In Proc. Asia and South Pacific Design Automation Conf., pages 97-100, Jan. 1999.
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Jason Cong , Zhigang Pan , Lei He , Cheng-Kok Koh , Kei-Yong Khoo, Interconnect design for deep submicron ICs, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.478-485, November 09-13, 1997, San Jose, California, United States
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CITED BY 5
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Charles Alpert , Chris Chu , Gopal Gandham , Miloš Hrkić , Jiang Hu , Chandramouli Kashyap , Stephen Quay, Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
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Christoph Bartoschek , Stephan Held , Dieter Rautenbach , Jens Vygen, Efficient generation of short and fast repeater tree topologies, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
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Christoph Bartoschek , Stephan Held , Dieter Rautenbach , Jens Vygen, Fast buffering for optimizing worst slack and resource consumption in repeater trees, Proceedings of the 2009 international symposium on Physical design, March 29-April 01, 2009, San Diego, California, USA
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