Optimal reliable crosstalk-driven interconnect optimization

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Optimal reliable crosstalk-driven interconnect optimization

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International Symposium on Physical Design archive
Proceedings of the 2000 international symposium on Physical design table of contents

San Diego, California, United States

Pages: 128 - 133

Year of Publication: 2000

ISBN:1-58113-191-7

Authors

Iris Hui-Ru Jiang	Department of Electronics Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan
Song-Ra Pan	Department of Computer and Information Science, National Chiao Tung University, Hsinchu 30010, Taiwan
Yao-Wen Chang	Department of Computer and Information Science, National Chiao Tung University, Hsinchu 30010, Taiwan
Jing-Yang Jou	Department of Electronics Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 4, Citation Count: 2

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Chung-Ping Chen , Yao-Wen Chang , D. F. Wong, Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation, Proceedings of the 33rd annual conference on Design automation, p.405-408, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240596]
	2	Chung-Ping Chen , Chris C. N. Chu , D. F. Wong, Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.617-624, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.289097]
	3	Thomas T. Cormen , Charles E. Leiserson , Ronald L. Rivest, Introduction to algorithms, MIT Press, Cambridge, MA, 1990
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	6	Frederick S. Hillier , Gerald J. Lieberman, Introduction to operations research, 4th ed., Holden-Day, Inc., San Francisco, CA, 1986
	7	Hui-Ru Jiang , Jing-Yang Jou , Yao-Wen Chang, Noise-constrained performance optimization by simultaneous gate and wire sizing based on Lagrangian relaxation, Proceedings of the 36th ACM/IEEE conference on Design automation, p.90-95, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309882]
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	9	S. Malik, E. Sentovich, R. K. Brayton and A. Sangiovanni-Vincentelli, "Retiming and Resynthesis: Optimization of Sequential Networks with Combinational Techniques," IEEE Trans. on Computer Aided Design, 10(1), Jan. 1991.
	10	Satyamurthy Pullela , Noel Menezes , Lawrence T. Pillage, Reliable non-zero skew clock trees using wire width optimization, Proceedings of the 30th international conference on Design automation, p.165-170, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164653]
	11	Jan M. Rabaey, Digital integrated circuits: a design perspective, Prentice-Hall, Inc., Upper Saddle River, NJ, 1996
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	14	W. L. Winston, Operations Resealvh: Applications and Algorithms, 3rd ed., Thomson, 1994.

CITED BY 2

	Prashant Saxena , Satyanarayan Gupta, Shield count minimization in congested regions, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	Prashant Saxena , Kumar N. Lalgudi , Hans J. Greub , Janet M. Wang-Roveda, A perturbation-aware noise convergence methodology for high frequency microprocessors, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China

Collaborative Colleagues:

Iris Hui-Ru Jiang: colleagues

Song-Ra Pan: colleagues

Yao-Wen Chang: colleagues

Jing-Yang Jou: colleagues

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