Simulating frequency-dependent current distribution for inductance modeling of on-chip copper interconnects

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Simulating frequency-dependent current distribution for inductance modeling of on-chip copper interconnects

Full text

Pdf (62 KB)

Source

International Symposium on Physical Design archive
Proceedings of the 2000 international symposium on Physical design table of contents

San Diego, California, United States

Pages: 117 - 120

Year of Publication: 2000

ISBN:1-58113-191-7

Authors

Li-Fu Chang	Frequency Technology, Inc., 469 El Camino Real, Santa Clara, California
Keh-Jeng Chang
Robert Mathews	Frequency Technology, Inc., 469 El Camino Real, Santa Clara, California

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 23, Citation Count: 1

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/332357.332386 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	L. Chang et al., "A new modeling methodology for copper on-chip interconnects", to appear in the proceedings of 2000 International Symposium on Quality of Electronic Design (ISQED 2000).
	2	A. E. Ruehli, "Equivalent Circuit Models for Three Dimensional Multiconductor Systems", IEEE Transactions on Microwave Theory and Technology, MTT-22 (3), pp. 216-221, March 1974.
	3	L. Chang et al., "Frequency Dependence of Resistance and Inductance Effects in On-Chip Interconnects", to appear in the Proceedings of DesignCon Conference, Santa Clara, California, January 2000.
	4	Yehia Massoud , Steve Majors , Tareq Bustami , Jacob White, Layout techniques for minimizing on-chip interconnect self inductance, Proceedings of the 35th annual conference on Design automation, p.566-571, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277194]
	5	L. Chang et al., "Modeling and Managing On-Chip Interconnect Inductance", Proceedings of VLSI Multilevel Interconnection Conference, pp. 457-462, September 1999.
	6	Ansoft Corp., Maxwell SpiceLink Software, 1999.
	7	J. White et al., FastHenry Software, 1992.
	8	K. Chang et al., "System and Method for Extracting Parasitic Impedance from an Integrated Circuit Layout", United States Patent 5901063, May 4, 1999.

CITED BY

Yehia Massoud , Jacob White, Simulation and modeling of the effect of substrate conductivity on coupling inductance and circuit crosstalk, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.286-291, June 2002

INDEX TERMS

Keywords:
cladding material, copper interconnect, electromagnetic field solvers, skin-effect current distribution

Collaborative Colleagues:

Li-Fu Chang: colleagues

Keh-Jeng Chang: colleagues

Robert Mathews: colleagues

Adobe Acrobat

QuickTime

Windows Media Player

Real Player