A performance optimization method by gate sizing using statistical static timing analysis

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A performance optimization method by gate sizing using statistical static timing analysis

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International Symposium on Physical Design archive
Proceedings of the 2000 international symposium on Physical design table of contents

San Diego, California, United States

Pages: 111 - 116

Year of Publication: 2000

ISBN:1-58113-191-7

Authors

Masanori Hashimoto	Dept. Communications & Computer Engineering, Kyoto University, Sakyo-ku, Kyoto, 606-8501, Japan
Hidetoshi Onodera	Dept. Communications & Computer Engineering, Kyoto University, Sakyo-ku, Kyoto, 606-8501, Japan

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 20, Citation Count: 6

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	H.-F. Jyu, S. Malik, S. Devadas and K. W. Keutzer, "Statistical Timing Analysis of Combinational Logic Circuits," IEEE Trans. VLSI Systems, Vol. 1, No. 2, pp. 126-137, June 1993.
	2	Rung-Bin Lin , Meng-Chiou Wu, A New Statistical Approach to Timing Analysis of VLSI Circuits, Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing, p.507, January 04-07, 1998
	3	R. B. Brashear, N. Menezes, C. Oh, L. T. Pillage and M. R. Mercer, "Predicting Circuit Performance Using Circuitlevel Statistical Timing Analysis," Proc. European Design and Test Conference, pp.332-337, 1994.
	4	M. Berkelaar, "Statistical Delay Calculation, a Linear Time Method," Proc. TAU, pp. 15-24, 1997.
	5	E. T. A. F. Jacobs , M. R. C. M. Berkelaar, Gate sizing using a statistical delay model, Proceedings of the conference on Design, automation and test in Europe, p.283-291, March 27-30, 2000, Paris, France [doi>10.1145/343647.343782]
	6	R.B. Hitchcock, G. L. Smith and D. D. Cheng, "Timing Analysis of Computer Hardware," IBM Journal of Research and Development, Vol. 26, No. 1, pp. 100-105, January 1982.
	7	Olivier Coudert, Gate sizing for constrained delay/power/area optimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.5 n.4, p.465-472, Dec. 1997 [doi>10.1109/92.645073]
	8	De-Sheng Chen , Majid Sarrafzadeh, An exact algorithm for low power library-specific gate re-sizing, Proceedings of the 33rd annual conference on Design automation, p.783-788, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240666]
	9	M. Hashimoto, H. Onodera, and K. Tamaru, "A Power and Delay Optimization Method using Input Reordering in Cell-Based CMOS Circuits," IEICE Trans. Fundamentals, Vol. E82-A, No. 1, pp. 159-166, January 1999.
	10	Synopsys Inc., Desigin Compiler Reference Manual, 1999.

CITED BY 6

	J. Dambre , D. Stroobandt , J. Van Campenhout, A probabilistic approach to clock cycle prediction, Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems, December 02-03, 2002, Monterey, California, USA
	Kenichi Okada , Kento Yamaoka , Hidetoshi Onodera, A statistical gate delay model for intra-chip and inter-chip variabilities, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	V. Mahalingam , N. Ranganathan , Justin E. Harlow, III, A novel approach for variation aware power minimization during gate sizing, Proceedings of the 2006 international symposium on Low power electronics and design, October 04-06, 2006, Tegernsee, Bavaria, Germany
	Kenichi Okada , Kento Yamaoka , Hidetoshi Onodera, A Statistical Gate-Delay Model Considering Intra-Gate Variability, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.908, November 09-13, 2003
	Osama Neiroukh , Xiaoyu Song, Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques, Proceedings of the conference on Design, Automation and Test in Europe, p.294-299, March 07-11, 2005
	V. Mahalingam , Nagarajan Ranganathan , Justin E. Harlow, A fuzzy optimization approach for variation aware power minimization during gate sizing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.8, p.975-984, August 2008

Collaborative Colleagues:

Masanori Hashimoto: colleagues

Hidetoshi Onodera: colleagues

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