Buffer minimization in pass transistor logic

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Buffer minimization in pass transistor logic

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International Symposium on Physical Design archive
Proceedings of the 2000 international symposium on Physical design table of contents

San Diego, California, United States

Pages: 105 - 110

Year of Publication: 2000

ISBN:1-58113-191-7

Authors

Hai Zhou	Advanced Technology Group, Synopsys, Inc., Mountain View, CA
Adnan Aziz	Department of ECE, University of Texas, Austin, TX

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 2, Downloads (12 Months): 10, Citation Count: 0

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references collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Robert K. Brayton , Gary D. Hachtel , Alberto L. Sangiovanni-Vincentelli , Fabio Somenzi , Adnan Aziz , Szu-Tsung Cheng , Stephen A. Edwards , Sunil P. Khatri , Yuji Kukimoto , Abelardo Pardo , Shaz Qadeer , Rajeev K. Ranjan , Shaker Sarwary , Thomas R. Shiple , Gitanjali Swamy , Tiziano Villa, VIS: A System for Verification and Synthesis, Proceedings of the 8th International Conference on Computer Aided Verification, p.428-432, August 03, 1996
	2	Premal Buch , Amit Narayan , A. Richard Newton , A. Sangiovanni-Vincentelli, Logic synthesis for large pass transistor circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.663-670, November 09-13, 1997, San Jose, California, United States
	3	Michael R. Garey , David S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman & Co., New York, NY, 1979
	4	Alok Jain , Randal E. Bryant, Inverter minimization in multi-level logic networks, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.462-465, November 07-11, 1993, Santa Clara, California, United States
	5	T. Kuroda and T. Sakurai, Overview of Low-Power ULSI Circuit Techniques. IEICE Trans. Electron., E78-C(4):334-343, April 1995.
	6	F.S. Lai and W. Hwang, Differential Cascade Voltage Switch with Pass-Gate (DCVSPG) Logic Tree for High Performance CMOS Digital Systems. International Symposium on VLSI Technology, Systems, and Applications, 1993.
	7	I-M. Liu, Personal communication. 1997.
	8	I-M. Liu, T.-H. Liu, H. Zhou, and A. Aziz, Simultaneous PTL Buffer Insertion and Sizing for Minimizing Elmore Delay. International Workshop on Logic Synthesis,, 1998.
	9	A. Parameswar, H. Hara, and T. Sakurai, A High Speed, Low Power, Swing Restored Pass-Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications. proc. Custom Integrated Circuits Conf., May 1994.
	10	Jan M. Rabaey, Digital integrated circuits: a design perspective, Prentice-Hall, Inc., Upper Saddle River, NJ, 1996
	11	T.S. Sheungm and K. Asada, Regenerative Pass-Transistor Logic: A Circuit Technique for High Speed Digital Design. IEICE Trans. Electron., E79-C(9):1274-1283, September 1996.
	12	Albert Ren Rui Wang, Algorithms for multilevel logic optimization, University of California at Berkeley, Berkeley, CA, 1991
	13	K. Yano, Y. Sasaki, K. Rikino, and K. Seki, Top-Down Pass-Transistor Logic Design. IEEE Journal of Solid-State Circuits, 31(6):792-803, June, 1996.
	14	K. Yano, T. Yamnaka, T. Nishida, M. Satio, K. Shimohigashi, and A. Shimizu, A 3.8-us CMOS 16x16-b Multiplier Using Complementary Pass-Transistor Logic. IEEE Journal of Solid-State Circuits, 25(2):388-395, April 1990.

Collaborative Colleagues:

Hai Zhou: colleagues

Adnan Aziz: colleagues

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