Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessor

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Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessor

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International Symposium on Physical Design archive
Proceedings of the 2000 international symposium on Physical design table of contents

San Diego, California, United States

Pages: 99 - 104

Year of Publication: 2000

ISBN:1-58113-191-7

Authors

Rory McInerney	Intel Corp., SC12-408
Kurt Leeper	Intel Corp., SC12-405
Troy Hill	Intel Corp., RA2-350
Heming Chan	Intel Corp., AN1
Bulent Basaran	Intel Corp., SC12-601
Lance McQuiddy	Intel Corp., SC12-405

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 19, Citation Count: 11

Additional Information:

cited by index terms collaborative colleagues

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CITED BY 11

	Pasquale Cocchini, Concurrent flip-flop and repeater insertion for high performance integrated circuits, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.268-273, November 10-14, 2002, San Jose, California
	Dennis Sylvester , Himanshu Kaul, Future performance challenges in nanometer design, Proceedings of the 38th conference on Design automation, p.3-8, June 2001, Las Vegas, Nevada, United States
	Rizwan Bashirullah , Wentai Liu , Ralph K. Cavin, III, Current-mode signaling in deep submicrometer global interconnects, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.3, p.406-417, June 2003
	Jason Cong , Yiping Fan , Zhiru Zhang, Architecture-level synthesis for automatic interconnect pipelining, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Himanshu Kaul , Dennis Sylvester, Low-power on-chip communication based on transition-aware global signaling (TAGS), IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.5, p.464-476, May 2004
	Raguraman Venkatesan , Jeffrey A. Davis , Keith A. Bowman , James D. Meindl, Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI), IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.6, p.899-912, 12/1/2001
	Liang Zhang , John Wilson , Rizwan Bashirullah , Lei Luo , Jian Xu , Paul Franzon, Driver pre-emphasis techniques for on-chip global buses, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	Navneeth Kankani , Vineet Agarwal , Janet Wang, A probabilistic analysis of pipelined global interconnect under process variations, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Rizwan Bashirullah , Wentai Liu , Ralph K. Cavin, Low-power design methodology for an on-chip bus with adaptive bandwidth capability, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Iris Hui-Ru Jiang , Yao-Wen Chang , Jing-Yang Jou , Kai-Yuan Chao, Simultaneous floorplanning and buffer block planning, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Himanshu Kaul , Dennis Sylvester , Mark A. Anders , Ram K. Krishnamurthy, Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.11, p.1225-1238, November 2005

INDEX TERMS

Keywords:
RC delay, estimation, floorplan, microprocessors, repeaters, routing, timing

Collaborative Colleagues:

Rory McInerney: colleagues

Kurt Leeper: colleagues

Troy Hill: colleagues

Heming Chan: colleagues

Bulent Basaran: colleagues

Lance McQuiddy: colleagues

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