| Wire packing: a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution |
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International Symposium on Physical Design
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Proceedings of the 2000 international symposium on Physical design
table of contents
San Diego, California, United States
Pages: 61 - 68
Year of Publication: 2000
ISBN:1-58113-191-7
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Authors
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Rony Kay
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Intel Corporation, Santa Clara, California
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Rob A. Rutenbar
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Dept. of ECE, Carnegie Mellon University, Pittsburgh, Pennsylvania
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Downloads (6 Weeks): 4, Downloads (12 Months): 19, Citation Count: 9
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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H.B. Bakoglu, Circuits Interconnections and Packaging for VLSI, Addison-Wesley, 1990
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K. Chaudhary, A. Onozawa, E.S. Kuh, "A Spacing Algorithm for Performance and Cross-talk Reduction", Proc, DAC., 1993
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J.A. Davis, V. K. De, J. D. Meindel, "A Stochastic Wire-Length Distribution for Gigascale Integration", IEEE TED, Mar 1998
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U. Feige , S. Goldwasser , L. Lovász , S. Safra , M. Szegedy, Approximating clique is almost NP-complete (preliminary version), Proceedings of the 32nd annual symposium on Foundations of computer science, p.2-12, September 1991, San Juan, Puerto Rico
[doi> 10.1109/SFCS.1991.185341]
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M.C. Golumbic, Algorithmic Graph Theo~?; and Perfect Graphs, Academic Press, 1980
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K. S. Jhan~, S. Ha, C. S. John, "COP: A Crosstalk Optimizer for Gridded Channel Routing", IEEE Trans. on CAD, Apr 1996
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Semiconductor Industry Association, "The National Technology Roadmap for Semiconductors", 1997
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Hsiao-Ping Tseng , Louis Scheffer , Carl Sechen, Timing and crosstalk driven area routing, Proceedings of the 35th annual conference on Design automation, p.378-381, June 15-19, 1998, San Francisco, California, United States
[doi> 10.1145/277044.277148]
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A. Vittal, M. Marek-Sadowska, "Crosstalk Reduction for VLSI", IEEE Trans. on Computer-Aided Design, Vol. 16, No. 3, Mar 1997
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T. Xue, E. S. Kuh, D. Wang, "Post Global Routing Crosstalk Synthesis", IEEE Trans. on Computer-Aided Design, Dec. 1997
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M. Yannakakis, "Expressing Combinatorial Optimization Problems by Linear Programs", J. of Computerand System Sci., 43, 1991.
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CITED BY 9
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Shabbir Batterywala , Narendra Shenoy , William Nicholls , Hai Zhou, Track assignment: a desirable intermediate step between global routing and detailed routing, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.59-66, November 10-14, 2002, San Jose, California
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