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Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization
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Source International Symposium on Physical Design archive
Proceedings of the 2000 international symposium on Physical design table of contents
San Diego, California, United States
Pages: 55 - 60  
Year of Publication: 2000
ISBN:1-58113-191-7
Authors
Lei He  University of Wisconsin, 1415 Engineering Drive, Madison, WI
Kevin M. Lepak  University of Wisconsin, 1415 Engineering Drive, Madison, WI
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 3,   Downloads (12 Months): 11,   Citation Count: 20
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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T. Xue and E. S. Kuh, "Post global routing corsstalk synthesis", IEEE Trans. CAD-16, no.12, pp. 1418-1430, Dec. 1997
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L. He and M. Xu, "Characteristics and Modeling for Onchip Inductive Coupling", U. of Wisconsin at Madison, Technical Report ECE-00-1.
 
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L. He, N. Chang, S. Lin, and O. S. Nakagawa, "An Efficient Inductance Modeling for On-Chip Interconnects", Proc. IEEE Custom Integrated Circuits Conference, pp. 457-460, May 1999.
 
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C. Sechen, "An improved simulated annealing algorithm for row-based placement", Proc. ICCAD, pp. 478-481, 1997.
 
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L. He and K. M. Lepak, "Simultaneous Shield Insertion and Net Ordering for Capacitive and Inductive Coupling Minimization", U. of Wisconsin at Madison, Technical Report ECE-00-2.

CITED BY  20