| Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization |
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International Symposium on Physical Design
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Proceedings of the 2000 international symposium on Physical design
table of contents
San Diego, California, United States
Pages: 55 - 60
Year of Publication: 2000
ISBN:1-58113-191-7
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Authors
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Lei He
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University of Wisconsin, 1415 Engineering Drive, Madison, WI
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Kevin M. Lepak
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University of Wisconsin, 1415 Engineering Drive, Madison, WI
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| Bibliometrics |
Downloads (6 Weeks): 3, Downloads (12 Months): 11, Citation Count: 20
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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T. Xue and E. S. Kuh, "Post global routing corsstalk synthesis", IEEE Trans. CAD-16, no.12, pp. 1418-1430, Dec. 1997
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L. He and M. Xu, "Characteristics and Modeling for Onchip Inductive Coupling", U. of Wisconsin at Madison, Technical Report ECE-00-1.
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L. He, N. Chang, S. Lin, and O. S. Nakagawa, "An Efficient Inductance Modeling for On-Chip Interconnects", Proc. IEEE Custom Integrated Circuits Conference, pp. 457-460, May 1999.
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C. Sechen, "An improved simulated annealing algorithm for row-based placement", Proc. ICCAD, pp. 478-481, 1997.
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L. He and K. M. Lepak, "Simultaneous Shield Insertion and Net Ordering for Capacitive and Inductive Coupling Minimization", U. of Wisconsin at Madison, Technical Report ECE-00-2.
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CITED BY 20
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Kaushik Gala , David Blaauw , Junfeng Wang , Vladimir Zolotov , Min Zhao, Inductance 101: analysis and design issues, Proceedings of the 38th conference on Design automation, p.329-334, June 2001, Las Vegas, Nevada, United States
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Jinjun Xiong , Jun Chen , James Ma , Lei He, Post global routing RLC crosstalk budgeting, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.504-509, November 10-14, 2002, San Jose, California
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Atsushi Kurokawa , Nobuto Ono , Tetsuro Kage , Hiroo Masuda, DEPOGIT: dense power-ground interconnect architecture for physical design integrity, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.517-522, January 27-30, 2004, Yokohama, Japan
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Tong Jing , Ling Zhang , Jinghong Liang , Jingyu Xu , Xianlong Hong , Jinjun Xiong , Lei He, A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
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Jingyu Xu , Xianlong Hong , Tong Jing , Ling Zhang , Jun Gu, A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.677-682, January 27-30, 2004, Yokohama, Japan
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Jingyu Xu , Xianlong Hong , Tong Jing , Ling Zhang , Jun Gu, A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design, Integration, the VLSI Journal, v.39 n.4, p.457-473, July 2006
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