Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion

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Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion

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International Symposium on Physical Design archive
Proceedings of the 2000 international symposium on Physical design table of contents

San Diego, California, United States

Pages: 33 - 38

Year of Publication: 2000

ISBN:1-58113-191-7

Authors

I-Min Liu	Electrical and Computer Engineering, The University of Texas at Austin, Austin, Texas
Tan-Li Chou	Strategic CAD Labs., Design Technology, Intel Corporation, Hillsboro, Oregon
Adnan Aziz	Electrical and Computer Engineering, The University of Texas at Austin, Austin, Texas
D. F. Wong	Computer Sciences, The University of Texas at Austin, Austin, Texas

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 76, Citation Count: 8

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 8

	Jeng-Liang Tsai , Tsung-Hao Chen , Charlie Chung-Ping Chen, Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Jeng-Liang Tsai , Charlie Chung-Ping Chen, Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Matthew R. Guthaus , Dennis Sylvester , Richard B. Brown, Clock buffer and wire sizing using sequential programming, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Yanfeng Wang , Qiang Zhou , Yici Cai , Jiang Hu , Xianlong Hong , Jinian Bian, Low power clock buffer planning methodology in F-D placement for large scale circuit design, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Wei-Chung Chao , Wai-Kei Mak, Low-power gated and buffered clock network construction, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.1, p.1-20, January 2008
	Rupak Samanta , Jiang Hu , Peng Li, Discrete buffer and wire sizing for link-based non-tree clock networks, Proceedings of the 2008 international symposium on Physical design, April 13-16, 2008, Portland, Oregon, USA
	Min Ni , Seda Ogrenci Memik, Early planning for clock skew scheduling during register binding, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Matthew R. Guthaus , Dennis Sylvester , Richard B. Brown, Clock tree synthesis with data-path sensitivity matching, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea

Collaborative Colleagues:

I-Min Liu: colleagues

Tan-Li Chou: colleagues

Adnan Aziz: colleagues

D. F. Wong: colleagues

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