| A new switch chip for IBM RS/6000 SP systems |
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Conference on High Performance Networking and Computing
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Proceedings of the 1999 ACM/IEEE conference on Supercomputing (CDROM)
table of contents
Portland, Oregon, United States
Article No. 16
Year of Publication: 1999
ISBN:1-58113-091-0
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Authors
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Craig B. Stunkel
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IBM T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY
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Jay Herring
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IBM Server Division, 522 South Road, Poughkeepsie, NY
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Bulent Abali
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IBM T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY
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Rajeev Sivaram
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IBM Server Division, 522 South Road, Poughkeepsie, NY
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| Bibliometrics |
Downloads (6 Weeks): 3, Downloads (12 Months): 23, Citation Count: 7
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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D. Dai and D. K. Panda, "Reducing Cache Invalidation Overheads in Wormhole DSMs Using Multidestination Message Passing," Proc. Int. Conf. on Parallel Processing, Aug. 1996, pp. I:138- 145.
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Manolis Katevenis , Panagiota Vatsolaki , Aristides Efthymiou, Pipelined memory shared buffer for VLSI switches, Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication, p.39-48, August 28-September 01, 1995, Cambridge, Massachusetts, United States
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L. M. Ni, "Should Scalable Parallel Computers Support Efficient Hardware Multicast?," Proc. ICPP Workshop on Challenges for Parallel Processing, Aug. 1995, pp. 2-7.
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I. D. Scherson and C.-H. Chien, "Least common ancestor networks," Proc. 7th Int. Parallel Processing Symp., 1993, pp. 507-513.
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Craig B. Stunkel , Dennis G. Shea , Bülent Abali , Monty Denneau , Peter H. Hochschild , Douglas Joseph , Ben J. Nathanson , Mickey Tsao , Philip R. Varker, Architecture and Implementation of Vulcan, Proceedings of the 8th International Symposium on Parallel Processing, p.268-274, April 01, 1994
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C. B. Stunkel, D. G. Shea, D. G. Grice, P. H. Hochschild, and M. Tsao, "The SP1 High-Performance Switch," Proc. Scalable High-Performance Computing Conf., pp. 150-157, May 1994.
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C. B. Stunkel , D. G. Shea , B. Aball , M. G. Atkins , C. A. Bender , D. G. Grice , P. Hochschild , D. J. Joseph , B. J. Nathanson , R. A. Swetz , R. F. Stucke , M. Tsao , P. R. Varker, The SP2 high-performance switch, IBM Systems Journal, v.34 n.2, p.185-204, 1995
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Craig B. Stunkel , Rajeev Sivaram , Dhabaleswar K. Panda, Implementing multidestination worms in switch-based parallel systems: architectural alternatives and their impact, Proceedings of the 24th annual international symposium on Computer architecture, p.50-61, June 01-04, 1997, Denver, Colorado, United States
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CITED BY 7
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Marco Galluzzi , Valentín Puente , Adrián Cristal , Ramón Beivide , José-Ángel Gregorio , Mateo Valero, A first glance at Kilo-instruction based multiprocessors, Proceedings of the 1st conference on Computing frontiers, April 14-16, 2004, Ischia, Italy
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Marco Galluzzi , Ramón Beivide , Valentin Puente , José-Ángel Gregorio , Adrian Cristal , Mateo Valero, Evaluating kilo-instruction multiprocessors, Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture, p.72-79, June 20-20, 2004, Munich, Germany
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