| Candidate subcircuits for functional module identification in logic circuits |
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Great Lakes Symposium on VLSI
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Proceedings of the 10th Great Lakes symposium on VLSI
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Chicago, Illinois, United States
Pages: 34 - 38
Year of Publication: 2000
ISBN:1-58113-251-4
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Authors
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Jennifer L. White
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Department of Computer Science and Engineering, Michigan State University
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Anthony S. Wojcik
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Department of Computer Science and Engineering, Michigan State University
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Moon-Jung Chung
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Department of Computer Science and Engineering, Michigan State University
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Travis E. Doom
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Department of Computer Science and Engineering, Wright State University
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ABSTRACT
Recovering functional information from existing hardware is a difficult problem in design automation. However, it is an important focus for designers attempting to redesign for expanded functionality or superior performance. Often, the only reliable information available about a piece of digital hardware is the hardware itself. Documentation, even if it is available, may be outdated or incorrect. Existing procedures are able to recover the transistor-level netlist, or a gate-level netlist from an existing implementation. The next step in this process is the gate-level to module-level transformation, the focus of this paper. We have designed a technique to enumerate all of the potential modules within a gate-level netlist so that their functional equivalence to known modules may be evaluated.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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