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A comparison of dual-rail pass transistor logic families in 1.5V, 0.18μm CMOS technology for low power applications
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Source Great Lakes Symposium on VLSI archive
Proceedings of the 10th Great Lakes symposium on VLSI table of contents
Chicago, Illinois, United States
Pages: 101 - 106  
Year of Publication: 2000
ISBN:1-58113-251-4
Authors
G. D. Gristede  IBM T.J. Watson Research Center, Yorktown Heights, N.Y.
Wei Hwang  IBM T.J. Watson Research Center, Yorktown Heights, N.Y.
Sponsors
Northwestern University : Northwestern University
SIGDA: ACM Special Interest Group on Design Automation
IEEE : Institute of Electrical and Electronics Engineers
Publisher
ACM  New York, NY, USA
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ABSTRACT

In this paper the results of an experimental comparison of popular pass-transistor logic families in 1.5V, 0.18µm CMOS technology using advanced CAD tools for circuit tuning and simulation are presented. The logic families were compared using an experimental setup designed to clarify the strengths and weaknesses of each family in a relative fashion and evaluate their individual performances under identical operating conditions. An automatic circuit tuner was used to help ensure that the test circuits from each logic family were operating at near optimum performance. It is shown that the Differential Cascode Voltage Switch with Pass-Gate (DCVSPG) logic family is the most robust with respect to an amalgamation of speed, power, area and physical design criteria. The methodology of using hybrid pass-transistor / static CMOS circuit styles is also presented.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
G. D. Gristede: colleagues
Wei Hwang: colleagues