| A comparison of dual-rail pass transistor logic families in 1.5V, 0.18μm CMOS technology for low power applications |
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Great Lakes Symposium on VLSI
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Proceedings of the 10th Great Lakes symposium on VLSI
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Chicago, Illinois, United States
Pages: 101 - 106
Year of Publication: 2000
ISBN:1-58113-251-4
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Authors
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G. D. Gristede
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IBM T.J. Watson Research Center, Yorktown Heights, N.Y.
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Wei Hwang
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IBM T.J. Watson Research Center, Yorktown Heights, N.Y.
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Downloads (6 Weeks): 5, Downloads (12 Months): 26, Citation Count: 1
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ABSTRACT
In this paper the results of an experimental comparison of popular pass-transistor logic families in 1.5V, 0.18µm CMOS technology using advanced CAD tools for circuit tuning and simulation are presented. The logic families were compared using an experimental setup designed to clarify the strengths and weaknesses of each family in a relative fashion and evaluate their individual performances under identical operating conditions. An automatic circuit tuner was used to help ensure that the test circuits from each logic family were operating at near optimum performance. It is shown that the Differential Cascode Voltage Switch with Pass-Gate (DCVSPG) logic family is the most robust with respect to an amalgamation of speed, power, area and physical design criteria. The methodology of using hybrid pass-transistor / static CMOS circuit styles is also presented.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Kerry Bernstein , Keith M. Carrig , Christopher M. Durham , Patrick R. Hansen , David Hogenmiller , Edward J. Nowak , Norman J. Rohrer, High speed CMOS design styles, Kluwer Academic Publishers, Norwell, MA, 1998
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3
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K. Yano, T. Yamanaka, T. Nishida, M. Sato, K. Shimohigashi and A. Shimizu, "A 3.8 ns CMOS 16 x 16 Multiplier using Complementary Pass-Gate Transistor Logic," IEEE Journal of Solid-State Circuits, vol. 25, 1990, pp. 385-388.
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4
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F.S. Lai and W. Hwang, " Differential Cascode Voltage Switch with Pass-Gate Logic Tree for High Performance CMOS Digital Systems " 1993 Int. Symp. VLSI Technology Systems Applications, 1993, pp. 358-362.
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5
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M. Suzuki, N. Ohkubo, T. Yamanaka, A. Shimizu and K. Sasaki, "A 1.5 ns 32b CMOS ALU in Double Pass-Transistor Logic," Dig. Tech. Papers, ISSCC, 1993, pp. 90-91.
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6
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A. Parameswar, H. Hara and T. Sakuri, "A Swing Restored Pass-Transistor Logic-Based Multiply and Accumulate Circuit for Multimedia Applications", IEEE J. Solid-State Circuits, Vol. 31, No. 6, pp. 804-809, June 1996.
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7
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D. Somasekhar and K. Roy, "Differential Current Switch Logic: A Low Power DCVS Logic Family",lEEE Z Solid- State Circuits, Vol. 31, No. 7, pp. 981-991, July 1996.
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8
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ES. Lai and W. Hwang, "Design and implementation of Differential Cascode Voltage Switch with Pass-Gate (DCVSPG) Logic Tree for High Performance Digital Systems",lEEE J. Solid-State Circuits, Vol. 32, No. 4, pp. 563-573, April 1997.
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9
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R. Zirnmermann and W. Fichtner,"Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic",IEEE J. Solid State Circuits, Vol. 32, No. 7, pp. 1079-1090, July 1997.
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10
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S. Yamashita, K. Yano, Y. Sasaki, Y. Akita, H. Chikata, K. Rikino and K. Seki, "Pass-transistor/CMOS Collaborated Logic: The Best of Both Worlds", 1997 Symposium on VLSI circuits, Digest of Tech. Papers, pp. 31-32, 1997.
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CITED BY
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S. V. Kosonocky , A. J. Bhavnagarwala , K. Chin , G. D. Gristede , A.-M. Haen , W. Hwang , M. B. Ketchen , S. Kim , D. R. Knebel , K. W. Warren , V. Zyuban, Low-power circuits and technology for wireless digital systems, IBM Journal of Research and Development, v.47 n.2-3, p.283-298, March 2003
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