Supporting system-level power exploration for DSP applications

ABSTRACT

System-level power exploration requires tools for estimation of the overall power consumed by a system, as well as a detailed breakdown of the consumption of its main functional blocks. We focus on power estimation for data-dominated systems specified as synchronous data-flows and implemented on a single-processor architecture. Our estimator is integrated within the Ptolemy design environment, and provides information to system designers on the power dissipated by every task in a given specification. Power estimation is based on instruction-level power models. We demonstrate the applicability of our tool on a few design examples and target architectures.

REFERENCES

• 1: E. Macil, M. Pedram, F. Somenzi, "High-Level Power Modeling, Estimation and Optimization," IEEE Transactions on Computer.Aided Design of Integrated Circuits and Sys~ terns, Vol. 17, No. 11, pp. 1061-1079, November 1998.
• 2: Luca Benini , Robin Hodgson , Polly Siegel, System-level power estimation and optimization, Proceedings of the 1998 international symposium on Low power electronics and design, p.173-178, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280881]
• 3: D. Kirovski, C. Lee, M. Potkonjak, W. Mangione-Smith, "Synthesis of Power Efficient Systems-on-Silicon," Asian " and South Pacific Design Automation Conference, pp. 557- 562, February 1998.
• 4: David Lidsky , Jan M. Rabaey, Early power exploration—a World Wide Web application, Proceedings of the 33rd annual conference on Design automation, p.27-32, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240523]
• 5: Tajana Šimunić , Luca Benini , Giovanni De Micheli, Cycle-accurate simulation of energy consumption in embedded systems, Proceedings of the 36th ACM/IEEE conference on Design automation, p.867-872, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.310090]
• 6: Yanbing Li , Jörg Henkel, A framework for estimation and minimizing energy dissipation of embedded HW/SW systems, Proceedings of the 35th annual conference on Design automation, p.188-193, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277097]
• 7: B. Lee, T.M. Parks , "Dataflow Process Networks," Proeeedings of the IEEE, pp. 773-799, May 1995.
• 8: Marcello Lajolo , Luciano Lavagno , Anand Raghunathan , Sujit Dey , Alberto Sangiovanni-Vincentelli, Efficient Power Estimation Techniques for HW/SW Systems, Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design, p.191, March 04-05, 1999
• 9: B. Lee, D. G. Messerschmitt, "Synchronous D~teL Flow," Proceedings of the IEEE, September 1987.
• 10: Vivek Tiwari , Sharad Malik , Andrew Wolfe , Mike Tien-Chien Lee, Instruction level power analysis and optimization of software, Journal of VLSI Signal Processing Systems, v.13 n.2-3, p.223-238, Aug./Sept. 1996 [doi>10.1007/BF01130407]
• 11: P. Laramie, "Instruction Level Power Analysis and Low Power Design Methodology of a Microprocessor," CS Master Thesia, University of California, Berkeley.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN

General Terms:
Experimentation, Performance