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Reducing bus transition activity by limited weight coding with codeword slimming
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Source Great Lakes Symposium on VLSI archive
Proceedings of the 10th Great Lakes symposium on VLSI table of contents
Chicago, Illinois, United States
Pages: 13 - 16  
Year of Publication: 2000
ISBN:1-58113-251-4
Authors
Vijay Sundararajan  Dept. of ECE University of Minnesota
Keshab K. Parhi  Dept. of ECE University of Minnesota
Sponsors
Northwestern University : Northwestern University
SIGDA: ACM Special Interest Group on Design Automation
IEEE : Institute of Electrical and Electronics Engineers
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 4,   Downloads (12 Months): 15,   Citation Count: 1
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ABSTRACT

Transitions on high capacitance busses in VLSI systems result in considerable power dissipation. Various coding schemes have been proposed in literature to encode the input signal in order to reduce the number of transitions. Number of transitions can be reduced by introducing redundancy in data transferred over the busses. For a given amount of redundancy there exists a lower bound on the average number of transitions. In this paper we derive a new coding scheme which leads to extremely practical techniques for bus transmission that reduce bus transitions to within 3.96-8.42% of the lower bound depending on the redundancy employed. There is also a net reduction in power dissipation ranging from 8.53-21.88% over an uncoded bus transmission scheme. This savings in power dissipation is identical to that for bus-invert coding per word transmitted the higher efficiency brought about by codeword slimming, however, results in shorter codewords than bus-invert coding which in turn results in higher energy efficiency in word transmission. Applications suitable for this new technique include systems relying on bit-serial implementation and systems with bit-parallel implementations where the cost of extra parallel-to-serial and serial-to-parallel data-format converters is marginal compared to the power savings obtained.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
D. Liu and C. Svensson, "Power Consumption Estimation in CMOS VLSI Chips," IEEE Journal of Solid State Circuits, vol. 29, no. 6, pp. 663---670, 1994.
 
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S. Wuytack, et al., "Global Communication and Memory Optimizing Transformations for Low Power Systems," in Proceedings of International Workshop on Low Power Design, (Napa, CA, USA), pp. 203-208, April 1994.
 
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M. Stan and W. Burleson, "Limited-Weight Codes for Low- Power I/O," Proceedings of International Workshop on Low Power Design, pp. 209-214, April 1991.
 
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K. K. Parhi, "Systematic synthesis of DSP data format converters using life-time analysis and forward-backward register allocation," IEEE Trans. Circuits And Systems H Analog and Digital Signal Processing, vol. 39, pp. 423--440, July. 1992.


Collaborative Colleagues:
Vijay Sundararajan: colleagues
Keshab K. Parhi: colleagues