Low power and high performance design challenges in future technologies

ABSTRACT

We discuss key barriers to continued scaling of supply voltage and technology for microprocessors to achieve low-power and high-performance. In particular, we focus on short-channel effects, device parameter variations, excessive subthreshold and gate oxide leakage, as the main obstacles dictated by fundamental device physics. Functionality of special circuits in the presence of high leakage, SRAM cell stability, bit line delay scaling, and power consumption in clocks & interconnects, will be the primary design challenges in the future. Soft error rate control and power delivery pose additional challenges. All of these problems are further compounded by the rapidly escalating complexity of microprocessor designs. The excessive leakage problem is particularly severe for battery-operated, high-performance microprocessors.

REFERENCES

• 1: Web sites: Intel Corp*, Digital Equipment Corp (Compaq), IBM.
• 2: Microprocessor Reports (MDR).
• 3: Gonzalez et al, IEEE Journal of Solid State Circuits, Aug 97.
• 4: M. Bohr et al, IEDM 96.
• 5: C. Wann et. al., IEEE Trans. Electron Dev, Oct 96.
• 6: S. Thompson et. al., 1998 Symp. VLSI Tech, Jun 98

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN

General Terms:
Design, Measurement, Performance

Keywords:
VLSI design, low-power design, memory, microprocessor