FPGA clock management for low power applications (poster abstract)

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FPGA clock management for low power applications (poster abstract)

Source

International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays table of contents

Monterey, California, United States

Page: 219

Year of Publication: 2000

ISBN:1-58113-193-3

Authors

Ian Brynjolfson
Zeljko Zilic

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Citation Count: 2

Additional Information:

cited by index terms collaborative colleagues

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CITED BY 2

	Saraju P. Mohanty , N. Ranganathan, Energy-efficient datapath scheduling using multiple voltages and dynamic clocking, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.2, p.330-353, April 2005
	Sébastien Pillement , Olivier Sentieys , Raphaël David, DART: a functional-level reconfigurable architecture for high energy efficiency, EURASIP Journal on Embedded Systems, v.2008 n.1, p.1-13, January 2008