Programmable memory blocks supporting content-addressable memory

ABSTRACT

The Embedded System Block (ESB) of the APEX E programmable logic device family from Altera Corporation includes the capability of implementing content addressable memory (CAM) as well as product term macrocells, ROM, and dual port RAM. In CAM mode each ESB can implement a 32 word CAM with 32 bits per word. In product term mode, each ESB has 16 macrocells built out of 32 product terms with 32 literal inputs. The ability to reconfigure memory blocks in this way represents a new and innovative use of resources in a programmable logic device, requiring creative solutions in both the hardware and software domains. The architecture and features of this Embedded System Block are described.

REFERENCES

• 1: Altera Corporation, "Device Data Book", 1999
• 2: http ://www.altera.eom/
• 3: Altera Corporation, "APEX 20K Programmable Logic Device Family, Data Sheer', 1999.
• 4: Tony Stansfield , Ian Page, The Design of a New FPGA Architecture, Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications, p.1-14, September 01, 1995
• 5: Steven J. E. Wilton , Jonathan Rose , Zvonko G. Vranesic, Memory-to-memory connection structures in FPGAs with embedded memory arrays, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.10-16, February 09-11, 1997, Monterey, California, United States [doi>10.1145/258305.258307]
• 6: S. Wilton, J. Rose and Z. Vranesic, " Memory/Logic Interconnect Flexibility in FPGAs with Large Embedded Memory Arrays," in CICC 96, the IEEE Custom Integrated Circuits Conf., San Diego, CA, May 1996, pp. 144-147.
• 7: Frank Heile , Andrew Leaver, Hybrid product term and LUT based architectures using embedded memory blocks, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.13-16, February 21-23, 1999, Monterey, California, United States [doi>10.1145/296399.296415]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Logic arrays

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

General Terms:
Design, Performance