Characterizing the Storage Process and Its Effect on the Update of Main Memory by Write Through

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Characterizing the Storage Process and Its Effect on the Update of Main Memory by Write Through

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Journal of the ACM (JACM) archive
Volume 26 , Issue 1 (January 1979) table of contents

Pages: 6 - 27

Year of Publication: 1979

ISSN:0004-5411

Author

Alan Jay Smith

Computer Science Division, Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 5, Downloads (12 Months): 29, Citation Count: 14

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 14

	Norman P. Jouppi, Cache write policies and performance, ACM SIGARCH Computer Architecture News, v.21 n.2, p.191-201, May 1993
	Steven Przybylski, The performance impact of block sizes and fetch strategies, ACM SIGARCH Computer Architecture News, v.18 n.3a, p.160-169, June 1990
	Y.-C. Chen , A. V. Veidenbaum, An effective write policy for software coherence schemes, Proceedings of the 1992 ACM/IEEE conference on Supercomputing, p.661-672, November 16-20, 1992, Minneapolis, Minnesota, United States
	Lishing Liu, Cache designs with partial address matching, Proceedings of the 27th annual international symposium on Microarchitecture, p.128-136, November 30-December 02, 1994, San Jose, California, United States
	James G. Thompson , Alan Jay Smith, Efficient (stack) algorithms for analysis of write-back and sector memories, ACM Transactions on Computer Systems (TOCS), v.7 n.1, p.78-117, Feb. 1989
	P. Sweazey , A. J. Smith, A class of compatible cache consistency protocols and their support by the IEEE futurebus, ACM SIGARCH Computer Architecture News, v.14 n.2, p.414-423, June 1986
	W. C. Yen , K. S. Fu, Analysis of multiprocessor cache organizations with alternative main memory update policies, Proceedings of the 8th annual symposium on Computer Architecture, p.89-105, May 12-14, 1981, Minneapolis, Minnesota, United States
	Gabriel M. Silberman, Stack processing techniques in delayed-staging storage hierarchies, Communications of the ACM, v.26 n.11, p.999-1007, Nov. 1983
	Jeffrey D. Gee , Alan Jay Smith, The effectiveness of caches for vector processors, Proceedings of the 8th international conference on Supercomputing, p.333-343, July 11-15, 1994, Manchester, England
	Afzal Malik , Bill Moyer , Roger Zhou, Embedded cache architecture with programmable write buffer support for power and performance flexibility, Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, October 08-11, 2002, Grenoble, France
	Phil C. C. Yeh , Janak H. Patel , Edward S. Davidson, Performance of shared cache for parallel-pipelined computer systems, ACM SIGARCH Computer Architecture News, v.11 n.3, p.117-123, June 1983
	John Tse , Alan Jay Smith, CPU Cache Prefetching: Timing Evaluation of Hardware Implementations, IEEE Transactions on Computers, v.47 n.5, p.509-526, May 1998
	Alan Jay Smith, Cache Memories, ACM Computing Surveys (CSUR), v.14 n.3, p.473-530, Sept. 1982
	Jelena Trajkovic , Alexander V. Veidenbaum , Arun Kejariwal, Improving SDRAM access energy efficiency for low-power embedded systems, ACM Transactions on Embedded Computing Systems (TECS), v.7 n.3, p.1-21, April 2008