Principles of design automatioon system for very large scale computer design

ABSTRACT

The paper describes the outline of the design automation system which provides the following design methods: Higher level structural drawings capable of expressing designs with Boolean equations and truth tables. Function level logic simulation of the entire computer design with extensive use of function test programs Automated logic synthesis generating detailed logic just as designers expect Delay check promising the most truthful timing evaluation at each design stage in progress Highly automated physical design and diagnosis data generation The latest very large scale general purpose computer HITACHI M-680H/682H utilizes these methods to successfully reduce its development time.

REFERENCES

• 1: Y. 0hno, et.al., 'Design Verification of Large Scale LSI Computers',Proc ICCC 82, pp443-446, September 1982.
• 2: Masayuki Miyoshi , Yoshio Ooshima , Atsushi Sugiyama , Nobuhiko Onizuka , Nobutaka Amano, An extensive logic simulation method of very large scale computer design, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.360-365, July 1986, Las Vegas, Nevada, United States
• 3: Yooji Tsuchiya , Masato Morita , Yukio Ikariya , Eiichi Tsurumi , Teruo Mori , Tamoatsu Yanagita, Establishment of higher level logic design for very large scale computer, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.366-371, July 1986, Las Vegas, Nevada, United States
• 4: Reiji Toyoshima , Yoshimitsu Takiguchi , Kazumi Matsumoto , Hidetomo Hongou , Mashiro Hashimoto , Ryotaro Kamikawai , Katsuhiko Takizawa, An effective delay analysis system for a large scale computer design, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.398-403, July 1986, Las Vegas, Nevada, United States
• 5: Yasushi Ogawa , Tatsuki Ishii , Yoichi Shiraishi , Hidekazu Terai , Tokinori Kozawa , Kyoji Yuyama , Kyoji Chiba, Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.404-410, July 1986, Las Vegas, Nevada, United States
• 6: T. Shinsha , T. Kubo , Y. Sakataya , J. Koshishita , K. Ishihara, Incremental logic synthesis through gate logic structure identification, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.391-397, July 1986, Las Vegas, Nevada, United States
• 7: K. Kishida , F. Shirotori , Y. Ikemoto , S. Ishiyama , T. Hayashi, A delay test system for high speed logic LSI's, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.786-790, July 1986, Las Vegas, Nevada, United States

INDEX TERMS

Primary Classification:
  J. Computer Applications

Additional Classification:
  C. Computer Systems Organization
  C.5 COMPUTER SYSTEM IMPLEMENTATION

General Terms:
Design, Measurement, Performance, Theory, Verification