A heuristic chip-level test generation algorithm

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A heuristic chip-level test generation algorithm

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 23rd ACM/IEEE Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 257 - 262

Year of Publication: 1986

ISBN:0-8186-0702-5

Authors

Daniel S. Barclay	Electrical Engineering Department, Virginia Tech, Blacksburg, VA
James R. Armstrong	Electrical Engineering Department, Virginia Tech, Blacksburg, VA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Press Piscataway, NJ, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 1, Citation Count: 7

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

An algorithm is given for generating tests from chip-level functional descriptions. The algorithm uses a chip-level fault model to define faults and fault sensitization requirements, and uses the hardware description language (HDL) definition to solve for the test vector. Artificial intelligence techniques of goal trees and rule databases are use to implement the algorithm in ProLog. The goal types and solving strategies are outlined. The current, partial ProLog implementation is discussed.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	J. R. Armstrong, "Chip Level Modeling with Hardware Description Languages," Submitted to Desisn and Test.
	2	A. K. Gupta, "Functional Fault Modeling and Test Vector Development for VLSI Systems," Masters Thesis, E. E. Department, VA Tech, March, 1985.
	3	Anil K. Gupta , James R. Armstrong, Functional fault modeling and simulation for VLSI devices, Proceedings of the 22nd ACM/IEEE conference on Design automation, p.720-726, June 1985, Las Vegas, Nevada, United States [doi>10.1145/317825.317969]
	4	S. Sathe, "Functional Fault Simulation for LSI Devices," Masters Thesis, E. E. Department, VA Tech, June, 1982.
	5	S. M. Thatte and J. A. Abraham, "Test Generation for Microprocessors," IEEE Transactions on Computers, Vol. C-29, No. 6.
	6	J. Galliay, et al., "Physical vs. Logical Fault Models in MOS LSI Circuits: Impact on Their Testability," IEEE Transactions on Computers, Vol. C-29, pp. 527-531, June, 1980.
	7	VHDL User's Manual, Document No. IR-MD-065-1, August, 1985.

CITED BY 7

	F. E. Norrod, An automatic test generation algorithm for hardware description languages, Proceedings of the 26th ACM/IEEE conference on Design automation, p.429-434, June 25-28, 1989, Las Vegas, Nevada, United States
	P. C. Ward , J. R. Armstrong, Behavioral fault simulation in VHDL, Proceedings of the 27th ACM/IEEE conference on Design automation, p.587-593, June 24-27, 1990, Orlando, Florida, United States
	J.-F. Santucci , G. Dray , N. Giambiasi , M. Boumédine, A methodology to reduce the computational cost of behavioral test pattern generation, Proceedings of the 29th ACM/IEEE conference on Design automation, p.267-272, June 08-12, 1992, Anaheim, California, United States
	J. R. Armstrong, Chip-Level Modeling with HDLs, IEEE Design & Test, v.5 n.1, p.8-18, January 1988
	Jean François Santucci , Anne-lise Courbis , Norbert Giambiasi, Speed up of behavioral A.T.P.G. using a heuristic criterion, Proceedings of the 30th international conference on Design automation, p.92-96, June 14-18, 1993, Dallas, Texas, United States
	Chien-Hung Chao , F. Gail Gray, Micro-operation perturbations in chip level fault modeling, Proceedings of the 25th ACM/IEEE conference on Design automation, p.579-582, June 12-15, 1988, Atlantic City, New Jersey, United States
	M. B. Santos , F. M. Gonçalves , I. C. Teixeira , J. P. Teixeira, RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems, Journal of Electronic Testing: Theory and Applications, v.17 n.3-4, p.311-319, June-August 2001