SLS—a fast switch level simulator for verification and fault coverage analysis

ABSTRACT

We describe SLS, a large capacity, high performance switch level simulator, developed to run on an IBM System/370 architecture, that uses a model which closely reflects the behavior of MOS circuits. This performance is the result of mixing a compiled model with the more traditional approach of event-driven simulation control, together with very efficient algorithms for evaluating the steady state response of the circuit. SLS is used for design verification/checking applications and for estimating fault coverage.

REFERENCES

• 1: Bryant, R.E., "An Aigoritlun for MOS Logic Simulation," Lamda Magazine, fourth quarter, 1980.
• 2: Bryant, R.E., "A Switch-level Model and Simulator for MOS Digital Systems," 1EEE Transactions on Computers, February, 1984.
• 3: Schuster, M.D., and Bryant, R., "Concurrent Fault Simldation of MOS Digital Circuit,," 1984 Conference on Advanced Research in VLSI, M.I.T., 1984.
• 4: "CAE Stations' Simulators Tackle 1 Million Gates," Electronic Design, November, 1983.
• 5: Blank, T., "A Survey of Hardware Accelerators Used in Computer-Aided Design," 1EEE Design and Test of Computers, August, 1984.
• 6: Barzilai, Z., Huisman. L., Silberman, G.M., Tang, D.T. and Woo, L.S., "Simulating Pass Transistor Circuits Using Logic Simulation Machines," IEEE Design and Test of Computers, February, 1984.
• 7: Sunil K. Jain , Vishwani D. Agrawal, Test generation for MOS circuits using D-algorithm, Proceedings of the 20th conference on Design automation, p.64-70, June 27-29, 1983, Miami Beach, Florida, United States
• 8: AI-Arian, S.A., anti Agrawal, D.P., "Modeling and Testing of CMOS Circuits," Proceedings of 1984 ICCD Conference, October, 1984.
• 9: Barzilai, Z., lyengar, V.S., Rosen, B.K., and Silberman, G.M., "'Accurate Fault Modeling and Efficient Simulation of Differential CVS Ciruits," Proceedings of the International Test Conference, November, 1985.
• 10: Spillinger, I., and Stlberman, G.M., "improving the Performance of a Switch-level Simulator Targeted for a Logic Simulation Machine," 4th Hungarian Computer Science Conference, Gyor, Hungary, July, 1985.
• 11: Barzilai, Z., Beece, D.K., Huisman, L.M., Iyengar, V.S., and Silberman, G.M., "SLS - A Fast Switch Level Simulator," IBM Research Report, Number 11787, December 3, 1985.
• 12: Ong, S., Chao, H.H., Tsai, M.-Y., Shih, F.W., Hou, J.C.L., Lewis, K.W., Tang, J.Y.-F., Trempel, C.A., Hadsell, R.W., McCormick, P.E., Davis, C.V., Diamond, A.L., Medve, T.J., Higham, J.P., and Yu, H.N., "Micro-370, A 32-Bit Single Chip Microprocessor," 1EEE ISSCC Digest of Technical Papers, February, 1986.

INDEX TERMS

Primary Classification:
  J. Computer Applications

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Simulation
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Memory technologies

General Terms:
Design, Experimentation, Measurement, Performance, Theory, Verification