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 REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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1
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A.J. de Geus, "Logic Synthesis and Optimization Benchmarks". The benchmarks are in Logic interchange Format (LIF) and are available from the author upon receipt of a magnetic tape or floppy diskette.
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2
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W. Quine, "The Problem of Simplifying Truth Functions", American Math Monthly, Vol. 59, No. 8, October 1952, pp. 521-531.
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3
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R. Mueller, and R. Urbano, "A Topological Method for the Determination of the Minimal Forms of a Bollean Function", IRE Transactions on Electronics and Computers, Vol. EC-5, No. 3, September 1956, pp. 126-132.
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4
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E. McCluskey, "Minimization of Boolean Functions", Bell Systems Technical Report, Vol. 35, No. 5, November 1956, pp. 1417-1444.
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5
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S.J. Hong, R. G. Cain and D. L. Ostapko, "MINI: A Heuristic Approach for Logic Minimization", IBM journal of Research and Development, Vol. 18, September 1974, pp. 443-458.
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6
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T. Sasao, "Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arrays", IEEE Transactions on computers, September 1981.
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7
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R.K. Brayton, C. McMullen, "The Decomposition ancl Factorization of Boolean Expressions", Proceedings of" the International Symposium on Circuits and Systems, 1982, pp. 49-$4.
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8
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9
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K. Bartlett, G. Hachtel, "Library Specific Optimization of Multilevel Combinational Logic", Proceedings of" the IEEE International Conference on Computer Design, October 1985.
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10
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J. Darringer, W. Joyner, L. Bermen, L. Trevillyan, "Logic Synthesis Through Local Transformations", IBM Journal of Research and Development, Vol. 25, July 1981, pp. 272-280.
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11
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D. Gregory, K. Bartlett, A. J. de Geus, "Automatic Generation of Combinatorial Logic from a Functional Specification", Proceedings of" the IEEE International Symposium on Circuits and Systems, May 1984, pp. 986-989.
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12
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T. Uehara, "A Knowledge-Based Logic Design System", IEEE Design and Test of Computers, October 1985.
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13
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K. Enomoto, S. Nakamura, T. Ogihara, and S. Mural, "LORES-2: A Logic Reorganization System", IEEE Design and Test of Computers, October 1985.
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14
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W.W. Cohen, K. Bartlett, A.J. de Geus, "Impact of Metarules in a Rule Based Expert System for Gate Level Optimization", Proceedings of the IEEE International Symposium on Circuits and Systems, May 1985, pp. 873-876.
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15
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A.J. de Geus, W.W. Cohen, "A Rule-Based System for Optimizing Combinational Logic", IEEE Design and Test of Computers, August 1985, pp. 22-32.
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16
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F. Brglez, H. Fujiwara, "Benchmarks for Automatic Test Vector Generation". The benchmarks have been put together for the 1985 International Symposium on Circuits and Systems and are available from the authors upon receipt of a magnetic tape.
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17
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R. Lisanke, F. Brglez, D. Gregory, A.J. de Geus, "T~stability-Driven Automatic Test Vector GeneraLion", Proceedings of the International Test Ce{iference, September 1986, pp. Submitted.
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18
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National Semiconductor, Logic DataBook, National Semiconductor, 1981.
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CITED BY 37
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W. N. Li , A. Lim , P. Agrawal , S. Sahni, On the circuit implementation problem, Proceedings of the 29th ACM/IEEE conference on Design automation, p.478-483, June 08-12, 1992, Anaheim, California, United States
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C.-F. E. Wu , A. S. Wojcik , L. M. Ni, A rule-based circuit representation for automated CMOS design and verification, Proceedings of the 24th ACM/IEEE conference on Design automation, p.786-792, June 28-July 01, 1987, Miami Beach, Florida, United States
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D. S. Kung , R. F. Damiano , T. A. Nix , D. J. Geiger, BDDMAP: a technology mapper based on a new covering algorithm, Proceedings of the 29th ACM/IEEE conference on Design automation, p.484-487, June 08-12, 1992, Anaheim, California, United States
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T.-T. Hwang , R. M. Owens , M. J. Irwin, Multi-level logic synthesis using communication complexity, Proceedings of the 26th ACM/IEEE conference on Design automation, p.215-220, June 25-28, 1989, Las Vegas, Nevada, United States
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W. P. Birmingham , A. P. Gupta , D. P. Siewiorek, The MICON system for computer design, Proceedings of the 26th ACM/IEEE conference on Design automation, p.135-140, June 25-28, 1989, Las Vegas, Nevada, United States
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Robert Francis , Jonathan Rose , Zvonko Vranesic, Chortle-crf: Fast technology mapping for lookup table-based FPGAs, Proceedings of the 28th conference on ACM/IEEE design automation, p.227-233, June 17-22, 1991, San Francisco, California, United States
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J. A. Beekman , R. M. Owens , M. J. Irwin, Mesh arrays and LOGICIAN: a tool for their efficient generation, Proceedings of the 24th ACM/IEEE conference on Design automation, p.357-362, June 28-July 01, 1987, Miami Beach, Florida, United States
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L. Stok , D. S. Kung , D. Brand , A. D. Drumm , L. N. Reddy , N. Hieter , D. J. Geiger , H. H. Chao , P. J. Osler , A. J. Sullivan, BooleDozer: logic synthesis for ASICs, IBM Journal of Research and Development, v.40 n.4, p.407-430, July 1996
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