Development of a timing analysis program for multiple clocked network

ABSTRACT

This paper describes the development of a timing analysis program for logic networks using both critical path and enumerative trace methods. The program utilizes the dynamic data structure of Pascal and its recursive computing power such that depth first search and breath first search can be carried out for delay calculations in a highly efficient manner. The program detects long and short paths between storage elements, setup and hold time violations of flip-flop, and minimum pulse width violations of clock signals.

REFERENCES

• 1: Lionel C. Bening , Thomas A. Lane , Curtis R. Alexander , James E. Smith, Developments in logic network path delay analysis, Proceedings of the 19th conference on Design automation, p.605-615, January 1982
• 2: Robert B. Hitchcock, Sr., Timing Verification and the Timing Analysis program, Proceedings of the 19th conference on Design automation, p.594-604, January 1982
• 3: Thomas M. McWilliams, Verification of timing constraints on large digital systems, Proceedings of the 17th conference on Design automation, p.139-147, June 23-25, 1980, Minneapolis, Minnesota, United States [doi>10.1145/800139.804523]
• 4: David J. Pilling , Henry B. Sun, Computer-aided prediction of delays in LSI logic systems, Proceedings of the 10th workshop on Design automation, p.182-186, June 25-27, 1973
• 5: Eiji Tamura , Kimihiro Ogawa , Toshio Nakano, Path delay analysis for hierarchical building block layout system, Proceedings of the 20th conference on Design automation, p.403-410, June 27-29, 1983, Miami Beach, Florida, United States

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Simulation

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN

  J. Computer Applications

General Terms:
Design, Measurement, Performance, Theory, Verification